24th Reconfigurable Architectures Workshop
Official website: raw.necst.it
May 29-30, 2017. Orlando, Florida USA

The 24th Reconfigurable Architectures Workshop (RAW 2017) will be held in Orlando, Florida USA in May 2017. RAW 2017 is associated with the 31st Annual IEEE International Parallel & Distributed Processing Symposium (IEEE IPDPS 2017) and is sponsored by the IEEE Computer Society and the Technical Committee on Parallel Processing. The workshop is one of the major meetings for researchers to present ideas, results, and on-going research on both theoretical and practical advances in Reconfigurable Computing.

A reconfigurable computing environment is characterized by the ability of underlying hardware architectures or devices to rapidly alter (often on the fly) the functionalities of their components and the interconnection between them to suit the problem at hand. The area has a rich theoretical tradition and wide practical applicability. There are several commercially available reconfigurable platforms (FPGAs and coarse-grained devices) and many modern applications (including embedded systems and HPC) use reconfigurable subsystems. An appropriate mix of theoretical foundations and practical considerations, including algorithms architectures, applications, technologies and tools, is essential to fully exploit the possibilities offered by reconfigurable computing. The Reconfigurable Architectures Workshop aims to provide a forum for creative and productive interaction for researchers and practitioners in the area.


Topics of interest

Architectures & CAD

  • Algorithmic Techniques and Mapping
  • Emerging Technologies (optical models, 3D Interconnects, devices)
  • Reconfigurable Accelerators
  • Embedded systems and Domain-Specific solutions (Digital Media, Gaming, Automotive applications)
  • FPGA-based MPSoC and Multicore
  • Distributed Systems & Networks
  • Wireless and Mobile Systems
  • Critical issues (Security, Energy efficiency, Fault-Tolerance)

Hot Topics in Reconfigurable Computing

  • Configurable Cloud
  • Heterogeneous Computing in Data Centers
  • Accelerating Data Center Workloads
  • FPGA-based Deep Learning
  • Accelerating Genomic Computations
  • Acceleration of Data Analytics
  • Reconfigurable Computing in the IoT era
  • Organic Computing, Biology-Inspired Solutions
  • Applications in Finance

Runtime & System Management

  • Run-Time Reconfiguration Models and Architectures
  • Autonomic computing systems
  • Operating Systems and High-Level Synthesis
  • High-Level Design Methods (Hardware/Software co-design, Compilers)
  • System Support (Soft processor programming)
  • Runtime Support
  • Reconfiguration Techniques (reusable artifacts)
  • Simulations and Prototyping (performance analysis, verification tools)

Paper Submission

All manuscripts will be reviewed by at least three members of the program committee. Submissions should be a complete manuscript or, in special cases, may be a summary of relevant work. Manuscript for full papers should be not exceed 8 single-spaced, double-column pages using 10-point size font on 8.5X11 inch pages (IEEE conference style) including references, figures and tables. Manuscript for short papers should be not exceed 4 single-space, double-column pages. Papers are to be submitted through EasyChair. Submitted papers should not have appeared in or be under consideration for a different workshop, conference or journal. It is also expected that all accepted papers (regular or short) will be presented at the workshop by one of the authors.


IEEE CS Press will publish the IPDPS symposium and workshop abstracts as a printed volume. Proceedings of the workshops are distributed at the conference and are submitted for inclusion in the IEEE Xplore Digital Library after the conference.

Important Dates

Abstract submission January 11, 2017 February 2, 2017
Submission deadline January 15, 2017 February 5, 2017 (final)
Decision notification March 1, 2017
Camera-Ready papers due March 15, 2017



Workshop Chairs

  • Marco D. Santambrogio, Politecnico di Milano, Italy
  • Ramachandran Vaidyanathan, Louisiana State University, USA

Program Chairs

  • Diana Goehringer, Ruhr-University Bochum, Germany
  • Donatella Sciuto, Politecnico di Milano, Italy

Program Vice Chairs

  • Dirk Stroobandt, Ghent University, Belgium
  • Francesca Palumbo, Università di Sassari, Italy
  • Ann Gordon-Ross, University of Florida, USA

Steering Committee

  • Juergen Becker, Karlsruhe Institute of Technology, Germany
  • Viktor K. Prasanna, University of Southern California, USA
  • Ramachandran Vaidyanathan, Louisiana State University, USA


  • Brian Veale, IBM, USA
  • Ivan Beretta, University of Westminster, UK

Program Committee

  • Marco Domenico Santambrogio, Politecnico di Milano
  • Ramachandran Vaidyanathan, Louisiana State University
  • Catalin Ciobanu, University of Amsterdam
  • Diana Goehringer, Ruhr-University Bochum
  • Donatella Sciuto, Politecnico di Milano
  • Viktor K. Prasanna, University of Southern California
  • Juergen Becker, Karlsruhe Institute of Technology
  • Ivan Beretta, University of Westminster
  • Michael Huebner, Ruhr-University Bochum
  • Ana Varbanescu, University of Amsterdam
  • Antonio Miele, Politecnico di Milano
  • Nele Mentens, KU Leuven
  • Christian Hochberger, Technische Universitat Darmstadt
  • Jose Coutinho, Imperial College of London
  • Philip Leong, The Chinese University of Hong Kong
  • Martin Langhammer, Altera
  • Mario Porrmann, Bielefeld University
  • Steve Wilton, University of British Columbia
  • Guy Gogniat, Universit√© de Bretagne Sud
  • Francesca Palumbo, Università di Sassari
  • Miriam Leeser, Northeastern University
  • Andreas Koch, Technische Universitat Darmstadt
  • Martin Herbordt, Boston University
  • Gayatri Mehta, University of North Texas
  • Dionisios Pnevmatikatos, FORTH-ICS & Technical University of Crete
  • Rene Cumplido, INAOE
  • Eddie Hung, Imperial College London
  • Brian Veale, IBM
  • Marco Rabozzi, Politecnico di Milano (webmaster)