23rd Reconfigurable Architectures Workshop
Official website: raw.necst.it
Monday and Tuesday, May 23-24, 2016. Chicago Hyatt Regency, Chicago, Illinois USA

The 23rd Reconfigurable Architectures Workshop (RAW 2016) will be held in Chicago, Illinois USA in May 2016. RAW 2016 is associated with the 30th Annual IEEE International Parallel & Distributed Processing Symposium (IEEE IPDPS 2016) and is sponsored by the IEEE Computer Society and the Technical Committee on Parallel Processing. The workshop is one of the major meetings for researchers to present ideas, results, and on-going research on both theoretical and practical advances in Reconfigurable Computing.

A reconfigurable computing environment is characterized by the ability of underlying hardware architectures or devices to rapidly alter (often on the fly) the functionalities of their components and the interconnection between them to suit the problem at hand. The area has a rich theoretical tradition and wide practical applicability. There are several commercially available reconfigurable platforms (FPGAs and coarse-grained devices) and many modern applications (including embedded systems and HPC) use reconfigurable subsystems. An appropriate mix of theoretical foundations and practical considerations, including algorithms architectures, applications, technologies and tools, is essential to fully exploit the possibilities offered by reconfigurable computing. The Reconfigurable Architectures Workshop aims to provide a forum for creative and productive interaction for researchers and practitioners in the area.

Advance Program (Download as PDF)

May 23, 2016
08.00 - 08.15	Registration
08.15 - 08.30	Opening
08.30 - 09.30	Keynote 1 (Peter Hofstee - IBM, Austin, TX, USA) (Download slides) (Watch keynote) Session chair: Marco Domenico Santambrogio, Politecnico di Milano, Italy
09.30 - 10.00	Short Paper Introduction Session Day 1 (Download slides) Session chair: Marco Domenico Santambrogio, Politecnico di Milano, Italy
13	Benedikt Janßen, Moataz Naserddin and Michael Hübner: A Hardware/Software Co-Design Approach for Control Applications with Static Real-Time Reallocation (Download Slides)
36	Giulia Guidi, Enrico Reggiani, Lorenzo Di Tucci, Gianluca Durelli, Michaela Blott, Marco D. Santambrogio: On How to Improve FPGA-Based Systems Design Productivity via SDAccel (Download slides)
14	Jones Y. Mori, Andre Werner, Florian Fricke and Michael Hübner: A rapid prototyping method to reduce the design time in commercial high-level synthesis tools (Download slides)
16	Salma Hesham, Diana Göhringer and Mohamed Abd El Ghany: ARTNoCs: An Evaluation Framework for Hardware Architectures of Real-Time NoCs (Download slides)
26	Amit Kulkarni, Elias Vansteenkiste, Dirk Stroobandt, Andreas Brokalakis and Antonios Nikitakis: A fully parameterized Virtual Coarse Grained Reconfigurable Array for High Performance Computing Applications (Download slides)
4	Anita Tino and Kaamran Raahemifar: Assessing Multi-Task Placement Algorithms in RCUs (Download Slides)
10.00 - 10.30	Coffee Break and Interactive Session Short Papers Day 1
10.30 - 11.45	Session 1: Application Mapping and Design Space Exploration Session chair: Brian Veale, IBM, USA
15	Lester Kalms and Diana Göhringer: Clustering and Mapping Algorithm for Application Distribution on a Scalable FPGA Cluster (Download Slides)
42	Syed Waqar Nabi and Wim Vanderbauwhede: A Fast and Accurate Cost Model for FPGA Design Space Exploration in HPC Applications (Download Slides)
2	Hyunsuk Nam and Roman Lysecky: Latency, Power, and Security Optimization in Distributed Reconfigurable Embedded Systems (Download slides)
11.45 - 12.15	Interactive Session 1
12.15 - 13.15	Lunch
13.15 - 14.55	Session 2: Applications Session chair: Steve Wilton, University of British Columbia, Canada
45	Daniel Llamocca and Daniel Aloi: A Reconfigurable Fixed-Point Architecture for Adaptive Beamforming (Download slides)
37	Aaron Mills, Phillip H. Jones and Joseph Zambreno: Parameterizable FPGA-based Kalman Filter Coprocessor Using Piecewise Affine Modeling (Download slides)
47	Chi Zhang, Ren Chen and Viktor Prasanna: High Throughput Large Scale Sorting on a CPU-FPGA Heterogeneous Platform (Download slides)
21	Juan Andrés Pérez-Celis, José Martínez-Carranza, Alicia Morales-Reyes, Claudia Feregrino-Uribe and René Cumplido: An FPGA Architecture to Accelerate the Burrows Wheeler Transform by Using a Linear Sorter
14.55 - 15.25	Interactive Session 2 and Coffee Break
15.25 - 16.40	Session 3: Processor Architectures Session chair: Rene Cumplido, INAOE, Mexiko
24	Mohamed El-Hadedy, Hristina Mihajloska, Danilo Gligoroski, Amit Kulkarni, Dirk Stroobandt and Kevin Skadron: A 16-bit Reconfigurable Encryption Processor for Pi-Cipher (Download slides)
35	Stephan Nolting, Guillermo Paya-Vaya, Florian Giesemann, Holger Blume, Sebastian Niemann and Christian Müller-Schloer: Dynamic Self-Reconfiguration of a MIPS-Based Soft-Processor Architecture
12	Steffen Vaas, Marc Reichenbach and Dietmar Fey: An Application-specific Instruction Set Processor for Power Quality Monitoring
16.40 – 17.00	Interactive Session 3
17.00 - 18.00	Panel (Download slides) Session chair: Marco Domenico Santambrogio, Politecnico di Milano, Italy
21.00 - 24.00	RAW 2016 social event at Kingstone Mines, 2548 North Halsted Street, Chicago, IL 60614. Sponsored by TOPIC.

May 24, 2016
08.30 - 09.30	IPDPS Keynote
09.30 - 10.00	Coffee Break
10.00 - 11.00	Keynote 2 (Patrick Lysaght - Xilinx, San Jose, CA, USA) Session chair: Juergen Becker, Karlsruhe Institute of Technology, Germany
11.00 - 11.25	Short Paper Introduction Session Day 2 Session chair: Emanuele Del Sozzo, Politecnico di Milano, Italy
44	Alexandra Kourfali and Dirk Stroobandt: Efficient Hardware Debugging using Parameterized FPGA Reconfiguration
10	Fynn Schwiegelshohn, Florian Kästner and Michael Hübner: Enabling Dynamic Reconfiguration of Numerical Methods for the Robotic Motion Control Task
28	Martin Letras, Raudel Hernández-León and Rene Cumplido: Hardware Architectures for Frequent Itemset Mining Based on Equivalence Classes Partitioning (Download Slides)
19	Fabiola Casasopra, Gea Bianchi, Gianluca C. Durelli and Marco D. Santambrogio: Parallel Protein Identification Using an FPGA-Based Solution
3	Nikolaos Stekas and Dirk van den Heuvel: Face recognition using Local Binary Patterns Histograms (LBPH) on an FPGA-based System on Chip (SoC)
11.25 - 11.55	Interactive Session Short Papers Day 2
11.55 - 13.10	Session 4: Scheduler and Runtime Systems Session chair: Claudia Feregrino, INAOE, Mexiko
23	Andrea Purgato, Davide Tantillo, Marco Rabozzi, Donatella Sciuto and Marco D. Santambrogio: Resource-Efficient Scheduling for Partially-Reconfigurable FPGA-based Systems (Download Slides)
31	Tajas Ruschke, Lukas Johannes Jung, Dennis Wolf and Christian Hochberger: Scheduler for Inhomogeneous and Irregular CGRAs with Support for Complex Control Flow
20	Jens Rettkowski, Philipp Wehner, Evgheni Cutiscev and Diana Goehringer: LinROS: A Linux-based Runtime System for Reconfigurable MPSoCs
13.10 - 14.15	Lunch
14.15 - 15.15	Keynote 3 (Dirk van den Heuvel - TOPIC Embedded Products, Eindhoven, the Netherlands) Session chair: Ramachandran Vaidyanathan, Louisiana State University, USA
15.15 - 15.45	Interactive session 4 and Coffee Break
15.45 - 17.00	Session 5: High Level Synthesis and Object-Oriented Programming Session chair: Diana Goehringer, Ruhr-University Bochum, Germany
17	Emanuele Del Sozzo, Andrea Solazzo, Antonio Miele and Marco D. Santambrogio: On the Automation of High Level Synthesis of Convolutional Neural Networks (Download slides)
18	Gianluca C. Durelli, Fabrizio Spada, Christian Pilato and Marco D. Santambrogio: Scala-based Domain-Specific Language for Creating Accelerator-based SoCs
22	Hongyuan Ding, Sen Ma, Miaoqing Huang and David Andrews: OOGen: An Automated Generation Tool for Custom MPSoC Architectures Based on Object-oriented Programming Methods (Download slides)
17.00 - 17.20	Interactive session 5
17.20 - 17.55	Award Session and Closing Remarks (Download slides)

Topics of interest

Paper Submission

All manuscripts will be reviewed by at least three members of the program committee. Submissions should be a complete manuscript or, in special cases, may be a summary of relevant work. The manuscript should be not exceed 10 single-spaced, double-column pages using 10-point size font on 8.5X11 inch pages (IEEE conference style) including references, figures and tables. Papers are to be submitted through EasyChair. Submitted papers should not have appeared in or be under consideration for a different workshop, conference or journal. It is also expected that all accepted papers (regular or poster) will be presented at the workshop by one of the authors.

Publication

IEEE CS Press will publish the IPDPS symposium and workshop abstracts as a printed volume. Proceedings of the workshops are distributed at the conference and are submitted for inclusion in the IEEE Xplore Digital Library after the conference. Selected papers from RAW 2016 will be invited for submission to a special issue on Reconfigurable Computing for the Journal of Parallel and Distributed Computing.

Important Dates

Abstract submission January 04, 2016 January 15, 2016
Submission deadline January 08, 2016 January 20, 2016
Decision notification February 12, 2016 February 16, 2016
Camera-Ready papers due March 7, 2016

Organization

 

Workshop Chairs

• Marco D. Santambrogio, Politecnico di Milano, Italy
• Ramachandran Vaidyanathan, Louisiana State University, USA

Program Chairs

• Diana Goehringer, Ruhr-University Bochum, Germany
• Steve Wilton, University of British Columbia, Canada

Program Vice-Chairs

• Software & Tools: Michaela Blott, Xilinx, Dublin, Ireland
• Architectures & Algorithms: Seda Memik, Northwestern University, IL, USA
• Reconfigurable Systems & Applications: Donatella Sciuto, Politecnico di Milano, Italy

Steering Committee

• Jurgen Becker, Karlsruhe Institute of Technology, Germany
• Viktor K. Prasanna, University of Southern California, USA
• Ramachandran Vaidyanathan, Louisiana State University, USA

Publicity

• Brian Veale, IBM, USA
• Kentaro Sano, Tohoku University, Japan
• Nikolaos Voros, Technological Institute of Western Greece, Greece

Program Committee

• Marco Domenico Santambrogio, Politecnico di Milano
• Ramachandran Vaidyanathan, Louisiana State University
• Michaela Blott, Xilinx
• Steve Wilton, University of British Columbia
• Seda Ogrenci-Memik, Northwestern University
• Diana Goehringer, Ruhr-University Bochum
• Donatella Sciuto, Politecnico di Milano
• Juergen Becker, Karlsruhe Institute of Technology
• Kyle Rupnow, Advanced Digital Sciences Center
• Andreas Koch, Technische Universitat Darmstadt
• Nikolaos Voros, Technological Educational Institute of Western Greece
• Dimitrios Soudris, National Technical University of Athens
• Eduardo de La Torre, Technical University of Madrid
• Thomas Hollstein, Tallinn University of Technology
• Antonio Miele, Politecnico di Milano
• Miriam Leeser, Northeastern University
• Michael Huebner, Ruhr-University Bochum
• Martin Langhammer, Altera
• Mario Porrmann, Bielefeld University
• Dirk Koch, University of Manchester
• Eddie Hung, Imperial College London
• Rene Cumplido, INAOE
• Akash Kumar, National University of Singapore
• Yi-Hua Yang, Xilinx
• Joydip Das, Achronix Semiconductor Corporation
• Guy Gogniat, Université de Bretagne Sud
• Dirk Stroobandt, Ghent University
• Ken Eguro, Microsoft Research
• Dionisios Pnevmatikatos, FORTH-ICS & Technical University of Crete
• Philip Leong, The Chinese University of Hong Kong
• Nachiket Kapre, Nanyang Technological University
• Kentaro Sano, Tohoku University
• Christian Hochberger, Technische Universitat Darmstadt
• Ivan Beretta, Imperial College London
• Brian F. Veale, IBM
• Mike Wirthlin, Brigham Young University
• Martin Herbordt, Boston University
• Nele Mentens, KU Leuven
• Marco Rabozzi, Politecnico di Milano (webmaster)
• Gianluca Durelli, Politecnico di Milano
• Ana Varbanescu, University of Amsterdam
• Brad Hutchings, Brigham Young University
• Jose Coutinho, Imperial College of London
• Gayatri Mehta, University of North Texas
• Bruce Cockburn, University of Alberta
• Liam Marnane, University College Cork
• Aaron Severance, VectorBlox Computing, Inc.
• Suhaib Fahmy, University of Warwick
• Lesley Shannon, Simon Fraser University
• Catalin Ciobanu, University of Amsterdam
• Francesca Palumbo, UNISS

Sponsors