Automatic Flow Selection and Quality-of-Result Estimation for FPGA Placement
Gary Grewal, Shawki Areibi, Ziad Abouwaimer, Matthew Westrik and Betty Zhao
Candidates:
Automatic Flow Selection and Quality-of-Result Estimation for FPGA Placement
Gary Grewal, Shawki Areibi, Ziad Abouwaimer, Matthew Westrik and Betty Zhao
Exploiting Decoupled OpenCL Work-Items with Data Dependencies on FPGAs: A Case Study
Javier Alejandro Varela, Norbert Wehn, Qian Liang and Songyin Tang
A Pipelined and Scalable Dataflow Implementation of Convolutional Neural Networks on FPGA
Marco Bacis, Giuseppe Natale, Emanuele Del Sozzo and Marco Domenico Santambrogio
Best Demo Award
Winners:
A Scalable Dataflow Implementation of Curran’s Approximation Algorithm
Anna Maria Nestorov, Enrico Reggiani, Marco Domenico Santambrogio, Pavel Burovskiy, Hristina Palikareva and Tobias Becker
An On-chip Memory Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA
Haruyoshi Yonekawa and Hiroki Nakahara
Candidates:
A Scalable Dataflow Implementation of Curran’s Approximation Algorithm
Anna Maria Nestorov, Enrico Reggiani, Marco Domenico Santambrogio, Pavel Burovskiy, Hristina Palikareva and Tobias Becker
An On-chip Memory Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA
Haruyoshi Yonekawa and Hiroki Nakahara
Exploiting FPGAs from Higher Level Languages A signal analysis case study
Luca Stornaiuolo, Alberto Parravicini, Gianluca Durelli and Marco Domenico Santambrogio
A Pipelined and Scalable Dataflow Implementation of Convolutional Neural Networks on FPGA
Marco Bacis, Giuseppe Natale, Emanuele Del Sozzo and Marco Domenico Santambrogio
Best Poster Award
Winners:
FAReP: Fragmentation-Aware Replacement Policy for Task Reuse on Reconfigurable FPGAs
Godwin Enemali, Adewale Adetomi and Tughrul Arslan
Candidates:
FAReP: Fragmentation-Aware Replacement Policy for Task Reuse on Reconfigurable FPGAs
Godwin Enemali, Adewale Adetomi and Tughrul Arslan
Clock Buffers, Nets, and Trees for On-chip Communication: A Novel Network Access Technique in FPGAs
Adewale Adetomi, Godwin Enemali and Tughrul Arslan
A Highly Scalable and Efficient Parallel Design of N-Body Simulation on FPGA
Emanuele Del Sozzo, Lorenzo Di Tucci and Marco Santambrogio