25th Anniversary of Reconfigurable Architectures Workshop
Official website: raw.necst.it
May 21-22 2018. Vancouver, British Columbia CANADA

The 25th Reconfigurable Architectures Workshop (RAW 2018) will be held in Vancouver, British Columbia CANADA in May 2018. RAW 2018 is associated with the 32nd Annual IEEE International Parallel & Distributed Processing Symposium (IEEE IPDPS 2018) and is sponsored by the IEEE Computer Society and the Technical Committee on Parallel Processing. The workshop is one of the major meetings for researchers to present ideas, results, and on-going research on both theoretical and practical advances in Reconfigurable Computing.

A reconfigurable computing environment is characterized by the ability of underlying hardware architectures or devices to rapidly alter (often on the fly) the functionalities of their components and the interconnection between them to suit the problem at hand. The area has a rich theoretical tradition and wide practical applicability. There are several commercially available reconfigurable platforms (FPGAs and coarse-grained devices) and many modern applications (including embedded systems and HPC) use reconfigurable subsystems. An appropriate mix of theoretical foundations and practical considerations, including algorithms architectures, applications, technologies and tools, is essential to fully exploit the possibilities offered by reconfigurable computing. The Reconfigurable Architectures Workshop aims to provide a forum for creative and productive interaction for researchers and practitioners in the area.

Topics of interest

Architectures & CAD

  • Algorithmic Techniques and Mapping
  • Emerging Technologies (optical models, 3D Interconnects, devices)
  • Reconfigurable Accelerators
  • Embedded systems and Domain-Specific solutions (Digital Media, Gaming, Automotive applications)
  • FPGA-based MPSoC and Multicore
  • Distributed Systems & Networks
  • Wireless and Mobile Systems
  • Critical issues (Security, Energy efficiency, Fault-Tolerance)

Hot Topics in Reconfigurable Computing

  • Configurable Cloud
  • Heterogeneous Computing in Data Centers
  • Accelerating Data Center Workloads
  • FPGA-based Deep Learning
  • Accelerating Genomic Computations
  • Acceleration of Data Analytics
  • Reconfigurable Computing in the IoT era
  • Organic Computing, Biology-Inspired Solutions
  • Applications in Finance

Runtime & System Management

  • Run-Time Reconfiguration Models and Architectures
  • Autonomic computing systems
  • Operating Systems and High-Level Synthesis
  • High-Level Design Methods (Hardware/Software co-design, Compilers)
  • System Support (Soft processor programming)
  • Runtime Support
  • Reconfiguration Techniques (reusable artifacts)
  • Simulations and Prototyping (performance analysis, verification tools)

Paper Submission

All manuscripts will be reviewed by at least three members of the program committee. Submissions should be a complete manuscript or, in special cases, may be a summary of relevant work. Manuscript for full papers should be not exceed 8 single-spaced, double-column pages using 10-point size font on 8.5X11 inch pages (IEEE conference style) including references, figures and tables. Manuscript for short papers should be not exceed 4 single-space, double-column pages. Papers are to be submitted through EasyChair. Submitted papers should not have appeared in or be under consideration for a different workshop, conference or journal. It is also expected that all accepted papers (regular or short) will be presented at the workshop by one of the authors.


IEEE CS Press will publish the IPDPS symposium and workshop abstracts as a printed volume. Proceedings of the workshops are distributed at the conference and are submitted for inclusion in the IEEE Xplore Digital Library after the conference.

Important Dates

Submission deadline February 9, 2018
Decision notification March 3, 2018
Camera-Ready papers due March 16, 2018



Workshop Chairs

  • Dirk Stroobandt, Ghent University, Belgium
  • Ken Eguro, Microsoft Research

Program Chairs

  • Marco D. Santambrogio, Politecnico di Milano, Italy
  • Diana Goehringer, TU Dresden, Germany

Steering Committee

  • Juergen Becker, Karlsruhe Institute of Technology, Germany
  • Viktor K. Prasanna, University of Southern California, USA
  • Ramachandran Vaidyanathan, Louisiana State University, USA

Steering Chair:

  • Viktor K. Prasanna, University of Southern California, USA

Publicity Co-Chairs

  • Brian Veale, IBM, USA
  • Ivan Beretta, University of Westminster, UK
  • Laura Nacci, Politecnico di Milano, Italy

Webmaster and submission Chair

  • Marco Rabozzi, Politecnico di Milano, Italy

Program Committee

  • Juergen Becker, Karlsruhe Institute of Technology
  • Ivan Beretta, Imperial College London
  • Michaela Blott, Xilinx
  • Catalin Ciobanu, University of Amsterdam
  • Bruce Cockburn, University of Alberta
  • Jose Coutinho, Imperial College of London
  • Rene Cumplido, INAOE
  • Ken Eguro, Microsoft Research
  • Suhaib Fahmy, University of Warwick
  • Diana Goehringer, TU Dresden, Germany
  • Guy Gogniat, Université de Bretagne Sud
  • Martin Herbordt, Boston University
  • Christian Hochberger, Technische Universitaet Darmstadt
  • Michael Huebner, Ruhr-University Bochum
  • Eddie Hung, Imperial College London
  • Andreas Koch, Technische Universitaet Darmstadt
  • Dirk Koch, University of Manchester
  • Akash Kumar, National University of Singapore
  • Martin Langhammer, Intel
  • Miriam Leeser, Northeastern University
  • Philip Leong, The Chinese University of Hong Kong
  • Gayatri Mehta, University of North Texas
  • Nele Mentens, KU Leuven
  • Antonio Miele, Politecnico di Milano
  • Seda Ogrenci-Memik, Northwestern University
  • Francesca Palumbo, UNISS
  • Dionisios Pnevmatikatos, FORTH-ICS & Technical University of Crete
  • Mario Porrmann, Bielefeld University
  • Viktor Prasanna, University of Southern California
  • Marco Domenico Santambrogio, Politecnico di Milano
  • Donatella Sciuto, Politecnico di Milano
  • Dimitrios Soudris, National Technical University of Athens
  • Dirk Stroobandt, Ghent University
  • Marco Rabozzi, Politecnico di Milano, Italy
  • Ramachandran Vaidyanathan, Louisiana State University
  • Wim Vanderbauwhede, University of Glasgow
  • Ana Varbanescu, University of Amsterdam
  • Brian F. Veale, IBM
  • Sara Vinco, Politecnico di Torino
  • Steve Wilton, University of British Columbia


We would like to express our sincere thanks to all those who have contributed to the success of the workshop. In particular, we would like to thank all the members of the program committee and reviewers for their valuable time and effort in the review process, and to provide constructive feedback to the authors. We also acknowledge the support of the IPDPS organizing committee and IEEE Computer Society in producing these proceedings. A special mention has to be done for the EXTRA EU project members. We do really want to thank the members of the EXTRA EU project ("Exploiting eXascale Technology with Reconfigurable Architectures" - http://extrahpc.eu/ - funded from the EU Horizon 2020 research and innovation programme under grant No 671653) for their support in organizing this edition of RAW. Finally, we thank all authors who contributed to this workshop, for submitting their manuscript and sharing their latest research results with the RAW community. We hope that you will find in these proceedings and workshop a valuable platform as well as source of information for your work.