Keynote Speech
Reconfigurable Accelerators for Big Data and Cloud
Peter Hofstee - IBM, Austin, TX, USA
Tuesday, May 23, 2016
Abstract
This presentation makes the case for adding shared-memory reconfigurable logic into standard multi-purpose dynamically allocated cloud infrastructure. We look at the opportunities for offloading network, storage, and compute related functions from the CPU to the reconfigurable logic. Next we discuss how reconfigurable logic can be used in Big Data infrastructure, and we present an end-to-end example that brings cloud, big data, and reconfigurable computing together.
About the speaker
H. Peter Hofstee (Ph.D. California Inst. of Technology, 1995) is a distinguished research staff member at the IBM Austin Research Laboratory, USA,
and a part-time professor in Big Data Systems at Delft University of Technology, Netherlands.
Peter is best known for his contributions to heterogeneous computer architecture as the chief architect of the Synergistic Processor Elements
in the Cell Broadband Engine processor, used in the Sony Playstation3 and the first supercomputer to reach sustained Petaflop operation.
After returning to IBM research in 2011 he has focused on optimizing the system roadmap for big data, analytics, and cloud, including the use of accelerated compute.
His early research work on coherently attached reconfigurable acceleration on Power 7 paved the way for the new coherent attach processor interface on POWER 8.
Peter is an IBM master inventor with more than 100 issued patents and a member of the IBM Academy of technology.