28th Reconfigurable Architectures Workshop
Official website: raw.necst.it
May 17th-18th 2021. Portland, Oregon, USA

The 28th Reconfigurable Architectures Workshop (RAW 2021) will be held in Portland, Oregon, USA in May 2021. RAW 2021 is associated with the 35th Annual IEEE International Parallel & Distributed Processing Symposium (IEEE IPDPS 2021) and is sponsored by the IEEE Computer Society and the Technical Committee on Parallel Processing. The workshop is one of the major meetings for researchers to present ideas, results, and on-going research on both theoretical and practical advances in Reconfigurable Computing.

A reconfigurable computing environment is characterized by the ability of underlying hardware architectures or devices to rapidly alter (often on the fly) the functionalities of their components and the interconnection between them to suit the problem at hand. The area has a rich theoretical tradition and wide practical applicability. There are several commercially available reconfigurable platforms (FPGAs and coarse-grained devices) and many modern applications (including embedded systems and HPC) use reconfigurable subsystems. An appropriate mix of theoretical foundations and practical considerations, including algorithms architectures, applications, technologies and tools, is essential to fully exploit the possibilities offered by reconfigurable computing. The Reconfigurable Architectures Workshop aims to provide a forum for creative and productive interaction for researchers and practitioners in the area.

Virtual RAW Program

Reminder about IPDPS 2021 registration: All papers in the workshop must have one author registered at full (non-student) fee. It is assumed that all attendees to the workshop will be registered with IPDPS 2021 to give access to the proceedings and to all live events and recorded sessions of the conference.

May 17th
Opening Session
8.00 AM PDTOpening of the conferenece Download slides
Machine Learning - Part 1
Session Chair: Diana Goehringer, TU Dresden
8.15 AM PDTRAW-17Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Lukas Frickenstein, Mohamed Badawy, Walter Stechele:BinaryCoP: Binary Neural Network-based COVID-19 Face-Mask Wear and Positioning Predictor on Edge Devices Download slides Video Link
8.25 AM PDTRAW-15Danielle Tchuinkou Kwadjo, Joel Mandebi Mbongue, Christophe Bobda:Exploring a Layer-specific Pre-implemented flow for Mapping CNN on FPGA Download slides Video Link
8.35 AM PDTRAW-11Timothy Martin, Gary Grewal, Shawki Areibi:A Machine Learning Approach to Predict Timing Delays During FPGA Placement Download slides Video Link
Machine Learning - Part 2
Session Chair: Emanuele Del Sozzo, Politecnico di Milano, Italy
9.15 AM PDTRAW-29Hirohisa Watanabe, Hiroki Matsutani:Accelerating ODE-Based Neural Networks on Low-Cost FPGAs Download slides Video Link
9.25 AM PDTRAW-28Hirohisa Watanabe, Mineto Tsukada, Hiroki Matsutani:An FPGA-Based On-Device Reinforcement Learning Approach using Online Sequential Learning Download slides Video Link
9.35 AM PDTRAW-25Lorenzo Farinelli, Daniele Valentino De Vincenti, Andrea Damiani, Luca Stornaiuolo, Rolando Brondolin, Marco Domenico Santambrogio, Donatella Sciuto:Plaster: an Embedded FPGA-based Cluster Orchestrator for Accelerated Distributed Algorithms Download slides Video Link
Keynote Session
Session Chair: Nele Mentens, Leiden University, The Netherlands, and KU Leuven, Belgium
10.00 AM PDTRAW-KeynoteAhmad-Reza Sadeghi:In Hardware We Trust? From TPMs to Enclave Computing on RISC-V
May 18th
Design Space Exploration and Design Automation
Session Chair: Guido Walter Di Donato, Politecnico di Milano, Italy
8.00 AM PDTRAW-9Daniele Paletti, Davide Conficconi, Marco Domenico Santambrogio:Dovado: An Open-Source Design Space Exploration Framework Download slides Video Link
8.10 AM PDTRAW-5Lukas Weber, Lukas Sommer, Leonardo Solis-Vasquez, Tobias Vincon, Christian Knödler, Arthur Bernhardt, Ilia Petrov, Andreas Koch:A Framework for the Automatic Generation of FPGA-based Near-Data Processing Accelerators in Smart Storage Systems Download slides Video Link
8.20 AM PDTRAW-6Renato Campos, João Cardoso:On Data Parallelism Code Restructuring for HLS Targeting FPGAs Download slides
Distributed and Cloud Computing
Session Chair: Rolando Brondolin, Politecnico di Milano, Italy
8.45 AM PDTRAW-14Philipp Holzinger, Daniel Reiser, Tobias Hahn, Marc Reichenbach:Fast HBM Access with FPGAs: Analysis, Architectures, and Applications Download slides
8.55 AM PDTRAW-3Mohamed Hassan, Peter Athanas:Graph Analytics on Hybrid System (GAHS) Case Study: PageRank Download slides
9.05 AM PDTRAW-7Joel Mandebi Mbongue, Sujan Kumar Saha, Christophe Bobda:Performance Study of Multi-tenant Cloud FPGAs Download slides Video Link
Architectures and Applications
Session Chair: Davide Conficconi, Politecnico di Milano, Italy
9.30 AM PDTRAW-21Najdet Charaf, Ahmed Kamaleldin, Martin Thümmler, Diana Göhringer:RV-CAP: Enabling Dynamic Partial Reconfiguration for FPGA-Based RISC-V System-on-Chip Download slides Video Link
9.40 AM PDTRAW-8Quentin Berthet, Andres Upegui, Laurent Gantel, Alexandre Duc, Giulia Traverso:An Area-Efficient SPHINCS+ Post-Quantum Signature Coprocessor Download slides Video Link
9.50 AM PDTRAW-18Jianyu Chen, Maurice Daverveldt, Zaid Al-Ars:FPGA Acceleration of the Zstd Compression Algorithm Download slides Video Link
Closing Session
10.15 AM PDTClosing of the conference Download slides

Topics of interest

Hot Topics

  • Configurable Cloud
  • Heterogeneous Computing in Data Centers
  • Accelerating Data Center Workloads
  • FPGA-based Deep Learning
  • Accelerating Genomic Computations
  • Accelerating Data Analytics
  • Reconfigurable Computing in the IoT era
  • Organic Computing, Biologically-Inspired Solutions
  • Applications in Finance

Architectures & CAD

  • Algorithmic Techniques and Mapping
  • Emerging Technologies (optical models, 3D Interconnects, devices)
  • Reconfigurable Accelerators
  • Embedded systems and Domain-Specific solutions (Digital Media, Gaming, Automotive applications)
  • FPGA-based MPSoC and Multicore
  • Distributed Systems & Networks
  • Wireless and Mobile Systems
  • Critical issues (Security, Energy efficiency, Fault-Tolerance)

Runtime/System Management

  • RunTime Reconfiguration Models
  • Autonomic computing systems
  • Operating Systems and High-Level Synthesis
  • High-Level Design Methods (Hardware/Software co-design, Compilers)
  • System Support (Soft processor programming)
  • Runtime Support
  • Reconfiguration Techniques (reusable artifacts)
  • Simulations and Prototyping (performance analysis, verification tools)

Paper Submission

All manuscripts will be reviewed by at least three members of the program committee in a single blind review process. Submissions reporting your latest results, exciting developments and, in special cases, summaries of relevant work are sought. Manuscripts for full papers should not exceed 8 single-spaced, double-column pages using 10-point font on 8.5 x 11 inch pages (IEEE conference style) including references, figures and tables. Manuscripts for short papers should not exceed 4 single-space, double-column pages. Papers are to be submitted through EasyChair. Submitted papers should not have appeared in or be under consideration for another workshop, conference or journal. It is also expected that all accepted papers (regular or short) will be presented at the workshop by one of the authors.


IEEE CS Press will publish the IPDPS symposium and workshop abstracts as a printed volume. Proceedings of the workshops are distributed at the conference and are submitted for inclusion in the IEEE Xplore Digital Library after the conference.

Important Dates

Submission deadline January 29, 2021 February 15, 2021
Decision notification February 19, 2021 March 1, 2021 March 15, 2021
Camera-Ready papers due March 15, 2021 March 20, 2021


Workshop Chair

Program Chair

  • Nele Mentens, Leiden University, The Netherlands, and KU Leuven, Belgium

Steering Committee

  • Juergen Becker, Karlsruhe Institute of Technology, Germany
  • Viktor K. Prasanna, University of Southern California, USA
  • Ramachandran Vaidyanathan, Louisiana State University, USA

Steering Chair

  • Viktor K. Prasanna, University of Southern California, USA

Publicity Co-Chairs

  • Brian Veale, IBM, USA
  • Christian Pilato, Politecnico di Milano, Italy
  • Kentaro Sano, RIKEN Center for Computational Science, Japan


  • Francesco Peverelli, Politecnico di Milano, Italy
  • Marco Rabozzi, Huxelerate Srl, Italy

Program Committee

  • Alexandra Kourfali, Stuttgart University
  • Amit Kulkarni, duagon AG
  • Ana Lucia Varbanescu, University of Amsterdam
  • Bohan Yang, Tsinghua University
  • Brian F. Veale, IBM
  • Bruce Cockburn, University of Alberta
  • Bruno Tiagoda Silva Gomes, Vrije Universiteit Brussel (VUB)
  • Christian Hochberger, TU Darmstadt
  • Christian Pilato, Politecnico di Milano
  • Diana Goehringer, TU Dresden
  • Dimitrios Soudris, National Technical University of Athens
  • Dionisios Pnevmatikatos, National Technical University of Athens
  • Dirk Koch, The University of Manchester
  • Emanuele Del Sozzo, Politecnico di Milano
  • Guy Gogniat, Université de Bretagne Sud - UEB
  • Johanna Sepulveda, Airbus Defence and Space GmbH
  • Josep Balasch, KU Leuven
  • Kentaro Sano, Riken R-CCS
  • Lorenzo DiTucci, Huxelerate SRL
  • Mario Porrmann, Osnabrueck University
  • Martin Herbordt, Boston University
  • Martin Langhammer, Intel
  • Michael Huebner, Brandenburg University of Technology Cottbus
  • Miriam Leeser, Northeastern University
  • Oliver Sinnen, University of Auckland
  • Qiang Liu, Tianjin University
  • Ricardo Chaves, IST / INESC-ID
  • Sara Vinco, Politecnico di Torino
  • Shaojun Wang, Harbin Institute of Technology
  • Shreejith Shanker, Trinity College Dublin
  • Yuichiro Shibata, Nagasaki University