26th Reconfigurable Architectures Workshop
Official website: raw.necst.it
May 20 2019. Rio de Janeiro, Brazil

The 26th Reconfigurable Architectures Workshop (RAW 2019) will be held in Rio de Janeiro, Brazil in May 2019. RAW 2019 is associated with the 33rd Annual IEEE International Parallel & Distributed Processing Symposium (IEEE IPDPS 2019) and is sponsored by the IEEE Computer Society and the Technical Committee on Parallel Processing. The workshop is one of the major meetings for researchers to present ideas, results, and on-going research on both theoretical and practical advances in Reconfigurable Computing.

A reconfigurable computing environment is characterized by the ability of underlying hardware architectures or devices to rapidly alter (often on the fly) the functionalities of their components and the interconnection between them to suit the problem at hand. The area has a rich theoretical tradition and wide practical applicability. There are several commercially available reconfigurable platforms (FPGAs and coarse-grained devices) and many modern applications (including embedded systems and HPC) use reconfigurable subsystems. An appropriate mix of theoretical foundations and practical considerations, including algorithms architectures, applications, technologies and tools, is essential to fully exploit the possibilities offered by reconfigurable computing. The Reconfigurable Architectures Workshop aims to provide a forum for creative and productive interaction for researchers and practitioners in the area.

Advance Program

May 20, 2019
08.00 - 08.30 Registration
08.30 - 09.30 Welcome & Keynote
Performance harvesting in the post Moore era
Luigi Carro - Universidade Federal Do Rio Grande Do Sul, Brasil
09.30 - 10.00 Short paper introductions
RAW07 Yosi Ben Asher and Esti Stein: Evaluation of Circuits On the Reconfigurable Mesh
RAW09 Mateus Saquetti, Guilherme Bueno, Weverton Cordeiro and José Rodrigo Azambuja: VirtP4: an Architecture for P4 Virtualization
RAW11 Marzhan Bekbolat, Sabina Kairatova, Ayan Shymyrbay and Kizheppatt Vipin: HBLast: An open-source FPGA library for DNA sequencing acceleration
RAW14 Jens Rettkowski, Safdar Mahmood, Diana Goehringer, Michael Huebner and Arij Shallufa: Inspection of Partial Bitstreams for FPGAs using Artificial Neural Networks
RAW15 Syed Waqar Nabi and Wim Vanderbauwhede: Smart-Cache: Optimising Memory Accesses for Arbitrary Boundaries and Stencils on FPGAs
RAW19 Anna Maria Nestorov, Alberto Scolari, Enrico Reggiani, Luca Stornaiuolo and Marco D. Santambrogio: A Case Study for an Accelerated DCNN on FPGA-based Embedded Distributed System
RAW20 Maurício Dias and Daniel Ferreira: Deep Learning in ReconfigurableHardware: A Survey
10.00 - 10.30 Coffee break with poster discussions
10.30 - 12.00 Oral Session I - Design Methods and Tools
RAW18 Zakarya Guettatfi, Marco Platzner, Omar Kermia and Abdelhakim Khouas: An Approach for Mapping Periodic Real-time Tasks to Reconfigurable Hardware
RAW21 Enrico Reggiani, Marco Rabozzi, Anna Maria Nestorov, Alberto Scolari, Luca Stornaiuolo and Marco Domenico Santambrogio: Pareto optimal design space exploration for accelerated CNN on FPGA
RAW05 Markus Weinhardt: High-Level Synthesis Oriented Restructuring of Functions with While Loops
12.00 - 13.30 Lunch
13.30 - 15.00 Oral Session II - Applications
RAW23 Theodore Winograd, Rabia Shahid and Kris Gaj: An Automated Scheduler-based Approach for the Development of Cryptoprocessors for Pairing-Based Cryptosystems
RAW12 Luca Stornaiuolo, Massimo Perini, Marco Domenico Santambrogio and Donatella Sciuto: FPGA-based Embedded System Implementation of Audio Signal Alignment
RAW08 Fabio Benevenuti, Eduardo Chielle, Jorge Tonfat, Lucas Tambara, Fernanda Lima Kastensmidt, Carlos Alberto Zaffari, João Baptista dos Santos Martins and Otávio Santos Cupertino Durão: Experimental Applications Based on SRAM-based FPGA for NanosatC-BR2 Scientific Mission
15.00 - 15.30 Coffee break with poster discussions
15.30 - 16.30 Oral Session III - CAD
RAW16 Florian Fricke, André Werner, Keyvan Shahin, Florian Werner and Michael Huebner Automatic Tool-Flow for Mapping Applications to an Application-Specific CGRA Architecture
RAW17 Dario Korolija and Mirjana Stojilovic: FPGA-Assisted Deterministic Routing for FPGAs
16.30 - 17.00 Closing discussion
17.00 Drinks

Topics of interest

Architectures & CAD

  • Algorithmic Techniques and Mapping
  • Emerging Technologies (optical models, 3D Interconnects, devices)
  • Reconfigurable Accelerators
  • Embedded systems and Domain-Specific solutions (Digital Media, Gaming, Automotive applications)
  • FPGA-based MPSoC and Multicore
  • Distributed Systems & Networks
  • Wireless and Mobile Systems
  • Critical issues (Security, Energy efficiency, Fault-Tolerance)

Hot Topics in Reconfigurable Computing

  • Configurable Cloud
  • Heterogeneous Computing in Data Centers
  • Accelerating Data Center Workloads
  • FPGA-based Deep Learning
  • Accelerating Genomic Computations
  • Acceleration of Data Analytics
  • Reconfigurable Computing in the IoT era
  • Organic Computing, Biology-Inspired Solutions
  • Applications in Finance

Runtime & System Management

  • Run-Time Reconfiguration Models and Architectures
  • Autonomic computing systems
  • Operating Systems and High-Level Synthesis
  • High-Level Design Methods (Hardware/Software co-design, Compilers)
  • System Support (Soft processor programming)
  • Runtime Support
  • Reconfiguration Techniques (reusable artifacts)
  • Simulations and Prototyping (performance analysis, verification tools)

Paper Submission

All manuscripts will be reviewed by at least three members of the program committee. Submissions should be a complete manuscript or, in special cases, may be a summary of relevant work. Manuscript for full papers should not exceed 8 single-spaced, double-column pages using 10-point size font on 8.5X11 inch pages (IEEE conference style) including references, figures and tables. Manuscript for short papers should not exceed 4 single-space, double-column pages. Papers are to be submitted through EasyChair. Submitted papers should not have appeared in or be under consideration for a different workshop, conference or journal. It is also expected that all accepted papers (regular or short) will be presented at the workshop by one of the authors.


IEEE CS Press will publish the IPDPS symposium and workshop abstracts as a printed volume. Proceedings of the workshops are distributed at the conference and are submitted for inclusion in the IEEE Xplore Digital Library after the conference.

Important Dates

Submission deadline January 25, 2019 January 4, 2019 February 8, 2019
Decision notification February 15, 2019 March 1, 2019
Camera-Ready papers due March 3, 2019 March 22, 2019


Workshop Chairs

  • Marco D. Santambrogio, Politecnico di Milano, Italy
  • Diana Goehringer, TU Dresden, Germany

Program Chairs

Steering Committee

  • Juergen Becker, Karlsruhe Institute of Technology, Germany
  • Viktor K. Prasanna, University of Southern California, USA
  • Ramachandran Vaidyanathan, Louisiana State University, USA

Steering Chair:

  • Viktor K. Prasanna, University of Southern California, USA

Publicity Co-Chairs

  • Brian Veale, IBM, USA
  • Ivan Beretta, University of Westminster, UK


  • Marco Rabozzi, Politecnico di Milano, Italy

Program Committee

  • Alexander Kroh, UNSW Sydney
  • Andreas Koch, Technische Universitaet Darmstadt
  • Brian F. Veale, IBM
  • Bruce Cockburn, University of Alberta
  • Catalin Ciobanu, University of Amsterdam
  • Christian Hochberger, Technische Universitaet Darmstadt
  • Diana Goehringer, TU Dresden
  • Dimitrios Soudris, National Technical University of Athens
  • Dionisios Pnevmatikatos, FORTH-ICS & Technical University of Crete
  • Dirk Koch, University of Manchester
  • Eddie Hung, Imperial College London
  • Fernanda Lima Kastensmidt, UFRGS
  • Gayatri Mehta, University of North Texas
  • Guy Gogniat, Université de Bretagne Sud
  • Hayden So, University of Hong Kong
  • Jeff Goeders, Brigham Young University
  • Kentaro Sano, RIKEN
  • Lingli Wang, State Key Laboratory of ASIC & System, Fudan University
  • Lorenzo Di Tucci, Politecnico di Milano
  • Marco Domenico Santambrogio, Politecnico di Milano
  • Marco Rabozzi, Politecnico di Milano
  • Mario Porrmann, Bielefeld University
  • Martin Herbordt, Boston University
  • Martin Langhammer, Intel
  • Michael Huebner, Brandenburg University of Technology
  • Nele Mentens, KU Leuven
  • Oliver Diessel, UNSW Sydney
  • Oliver Sinnen, University of Auckland
  • Qiang Liu, Tianjin University
  • Ramachandran Vaidyanathan, Louisiana State University
  • Sara Vinco, Politecnico di Torino
  • Seda Ogrenci-Memik, Northwestern University
  • Shaojun Wang, Harbin Institute of Technology
  • Yuichiro Shibata, Nagasaki University