27th Reconfigurable Architectures Workshop
Official website: raw.necst.it
May 18-19 2020. New Orleans, Louisiana, USA
The 27th Reconfigurable Architectures Workshop (RAW 2020) will be held in New Orleans, USA in May 2020. RAW 2020 is associated with the 34rd Annual IEEE International Parallel & Distributed Processing Symposium (IEEE IPDPS 2020) and is sponsored by the IEEE Computer Society and the Technical Committee on Parallel Processing. The workshop is one of the oldest platforms and a vibrant forum for researchers to present new ideas, fresh results, and on-going research into both theoretical and practical advances including novel innovations in Reconfigurable Computing.
A reconfigurable computing environment is characterized by the ability of underlying hardware architectures or devices to rapidly alter (often on the fly) the functionalities of their components and the interconnection between them to suit the problem at hand. The area has a rich theoretical tradition and wide practical applicability. There are several commercially available reconfigurable platforms (FPGAs and coarse-grained devices) and many modern applications (including embedded systems and HPC) use reconfigurable subsystems. An appropriate mix of theoretical foundations and practical considerations, including algorithms architectures, applications, technologies and tools, is essential to fully exploit the possibilities offered by reconfigurable computing. The Reconfigurable Architectures Workshop aims to provide a forum for creative and productive interaction for researchers and practitioners in the area. This year the workshop will also provide a platform for work in progress.
NEWS
As you may already know, the physical RAW meeting of this year has been cancelled due to the coronavirus outbreak. However, we will still have a virtual RAW program (vRAW20) with all the accepted papers. All the accepted papers will appear in the usual IPDPS Workshops Proceedings for RAW and will be available to the community via IEEE Xplore.
In addition, the RAW Steering Committee has decided to host a virtual presentation space for RAW20 from June this year. The virtual presentation space will be hosted on the RAW website and comprises the presentation slides for each accepted paper and, optionally, a recording of the authors’ presentations. We have decided against providing a discussion forum this year.
We are very sorry to have missed you in New Orleans this year, but we really hope to see you in the not too distant future and next year at RAW 2021.
Instructions for the authors' of accepted papers
To create the virtual presentation space, we ask the authors to prepare and submit presentation slides for your RAW20 paper by 31 May. Please provide either a PowerPoint or PDF version of your presentation slides.
If you would like to make a recording of your presentation available as well - up to 20 minutes in duration for a full paper and 10 minutes for a short paper - we would like you to send us a link to your recording. We will make this link available or host a copy of the recording if you prefer. Please note that the Steering Committee does not require you to make a recording of your presentation available.
Please email your presentation slides and link details to: Marco Rabozzi (marco.rabozzi@gmail.com) and Oliver Diessel (o.diessel@unsw.edu.au) before 1 June.
Virtual RAW Program
Register for free at the IPDPS website to get instructions on how to access papers and static presentations for vRAW: http://www.ipdps.org/ipdps2020/
| Sessions | |
| Acceleration | |
| RAW-07 | Johanna Rohde, Karsten Müller and Christian Hochberger: Improving HLS Generated Accelerators Through Relaxed Memory Access SchedulingDownload slides |
| RAW-15 | Dionysios Diamantopoulos, Mitra Purandare, Burkhard Ringlein and Christoph Hagleitner: PHRYCTORIA: A Messaging System for Transprecision OpenCAPI-attached FPGA AcceleratorsDownload slides |
| RAW-28 | Yuan Meng, Sanmukh Kuppannagari, Rachit Rajat, Ajitesh Srivastava, Rajgopal Kannan and Viktor Prasanna: QTAccel: A Generic FPGA based Design for Q-Table based Reinforcement Learning Accelerators Download slides |
| RAW-05 | Niklas Lindskog and Håkan Englund: Secure acceleration on cloud-based FPGAs - FPGA enclavesDownload slides - Video presentation |
| RAW-22 | Seung-Hun Chung and Tarek Abdelrahman: Optimizing OpenCL Kernels and Runtime for DNN Inference on FPGAs Download slides |
| Embedded | |
| RAW-02 | Jincheng Yu, Feng Gao, Jianfei Cao, Chao Yu, Zhaoliang Zhang, Zhengfeng Huang, Yu Wang and Huazhong Yang: CNN-based Monocular Decentralized SLAM on embedded FPGA Download slides |
| RAW-11 | Stephen Tridgell, David Boland, Philip Leong, Ryan Kastner, Alireza Khodamoradi and Siddhartha: Real-time Automatic Modulation Classification using RFSoC Download slides - Video presentation |
| RAW-04 | Martin Langhammer, Gregg Baeckler and Sergey Gribok: SpiderWeb - A High Perfomance NoC for FPGADownload slides |
| RAW-10 | Tingyu Zhou, Tieyuan Pan, Yiping Dong, Michael Meyer and Takahiro Watanabe: An Interval-based Mapping Algorithm for Multi-shape Tasks on Dynamic Partial Reconfigurable FPGAsDownload slides |
| RAW-12 | Jessica Leoni, Asia Ciallella, Luca Stornaiuolo, Marco Domenico Santambrogio and Donatella Sciuto: EMPhASIS: An EMbedded Public Attention Stress Identification System Download slides - Video presentation |
| RAW-18 | Youki Sada, Naoto Soga, Masayuki Shimoda, Akira Jinguji, Shimpei Sato and Hiroki Nakahara: Fast Monocular Depth Estimation on an FPGADownload slides |
| Machine learning | |
| RAW-14 | Spencer Valancius, Edward Richter, Ruben Purdy, Kris Rockowitz, Michael Inouye, Richelle Javier, Joshua Mack, Nirmal Kumbhare, Kaitlin Fair, John Mixter and Ali Akoglu: FPGA Based Emulation Environment for Neuromorphic Architectures Download slides - Video presentation |
| RAW-13 | Giorgia Fiscaletti, Marco Speziali, Luca Stornaiuolo, Marco Domenico Santambrogio and Donatella Sciuto: Hardware resources analysis of BNNs splitting for FARD-based multi-FPGAs Distributed SystemsDownload slides - Video presentation |
| RAW-17 | Qian Zhao, Yasuhiro Nakahara, Motoki Amagasaki, Masahiro Iida and Takaichi Yoshida: A Microcode-based Control Unit for Deep Learning ProcessorsDownload slides |
| Large-scale computation | |
| RAW-09 | Laurent Gantel, Alexandre Duc, Lucie Steiner, Fabien Vannel, Andres Upegui and Florent Gluck: A FPGA-Based Post-Processing and Validation Platform for Random Number Generators Download slides |
| RAW-21 | Lorenzo Di Tucci, Riyadh Baghdadi, Saman Amarasinghe and Marco Domenico Santambrogio: SALSA: A Domain Specific Architecture for Sequence Alignment Download slides |
| RAW-25 | Guido Walter Di Donato, Alberto Zeni, Lorenzo Di Tucci and Marco Domenico Santambrogio: BWaveR: Leveraging Succinct Data Structures for DNA Sequence Mapping on FPGA Download slides - Video presentation |
Hot Topics
- Configurable Cloud
- Heterogeneous Computing in Data Centers
- Accelerating Data Center Workloads
- FPGA-based Deep Learning
- Accelerating Genomic Computations
- Accelerating Data Analytics
- Reconfigurable Computing in the IoT era
- Organic Computing, Biologically-Inspired Solutions
- Applications in Finance
Architectures & CAD
- Algorithmic Techniques and Mapping
- Emerging Technologies (optical models, 3D Interconnects, devices)
- Reconfigurable Accelerators
- Embedded systems and Domain-Specific solutions (Digital Media, Gaming, Automotive applications)
- FPGA-based MPSoC and Multicore
- Distributed Systems & Networks
- Wireless and Mobile Systems
- Critical issues (Security, Energy efficiency, Fault-Tolerance)
Runtime/System Management
- RunTime Reconfiguration Models
- Autonomic computing systems
- Operating Systems and High-Level Synthesis
- High-Level Design Methods (Hardware/Software co-design, Compilers)
- System Support (Soft processor programming)
- Runtime Support
- Reconfiguration Techniques (reusable artifacts)
- Simulations and Prototyping (performance analysis, verification tools)
Paper Submission
All manuscripts will be reviewed by at least three members of the program committee. Submissions reporting your latest results, exciting developments and, in special cases, summaries of relevant work are sought. Manuscripts for full papers should not exceed 8 single-spaced, double-column pages using 10-point font on 8.5 x 11 inch pages (IEEE conference style) including references, figures and tables. Manuscripts for short papers should not exceed 4 single-space, double-column pages. Papers are to be submitted through EasyChair. Submitted papers should not have appeared in or be under consideration for another workshop, conference or journal. It is also expected that all accepted papers (regular or short) will be presented at the workshop by one of the authors.Organization
Workshop Co-Chairs
- Marco D. Santambrogio, Politecnico di Milano, Italy
- Yu Wang, Tsinghua University, Beijing, China
Program Co-Chairs
- Oliver Diessel, University of New South Wales, Australia
- Christophe Bobda, University of Florida, USA
Steering Committee
- Juergen Becker, Karlsruhe Institute of Technology, Germany
- Viktor K. Prasanna, University of Southern California, USA
- Ramachandran Vaidyanathan, Louisiana State University, USA
Steering Chair
- Viktor K. Prasanna, University of Southern California, USA
Publicity Co-Chairs
- Brian Veale, IBM, USA
- Ivan Beretta, University of Westminster, UK
Webmaster
- Marco Rabozzi, Politecnico di Milano, Italy
Program Committee
- Alexander Kroh, UNSW Sydney
- Brian F. Veale, IBM
- Bruce Cockburn, University of Alberta
- Catalin Ciobanu, University of Amsterdam
- Christian Hochberger, Technische Universitaet Darmstadt
- Christophe Bobda, University of Florida, USA
- Diana Goehringer, TU Dresden
- Dimitrios Soudris, National Technical University of Athens
- Dionisios Pnevmatikatos, FORTH-ICS & Technical University of Crete
- Dirk Koch, University of Manchester
- Donald Bailey, Massey University
- Eddie Hung, Imperial College London
- Emanuele Del Sozzo, Politecnico di Milano
- Fernanda Lima Kastensmidt, UFRGS
- Gayatri Mehta, University of North Texas
- Guy Gogniat, Université de Bretagne Sud
- Hayden So, University of Hong Kong
- Juergen Becker, Karlsruhe Institute of Technology
- Lorenzo Di Tucci, Politecnico di Milano
- Marco Domenico Santambrogio, Politecnico di Milano
- Marco Platzner, Paderborn University
- Marco Rabozzi, Politecnico di Milano
- Mario Porrmann, Bielefeld University
- Markus Weinhardt, Osnabrück University of Applied Sciences
- Martin Herbordt, Boston University
- Martin Langhammer, Intel
- Michael Huebner, Brandenburg University of Technology
- Miriam Leeser, Northeastern University
- Mirjana Stojilovic, EPFL
- Nele Mentens, KU Leuven
- Oliver Diessel, UNSW Sydney
- Qiang Liu, Tianjin University
- Ramachandran Vaidyanathan, Louisiana State University
- Sara Vinco, Politecnico di Torino
- Seda Ogrenci-Memik, Northwestern University
- Shaojun Wang, Harbin Institute of Technology
- Viktor Prasanna, University of Southern California
- Yu Wang, Tsinghua University
- Yuichiro Shibata, Nagasaki University