24th Reconfigurable Architectures Workshop
Official website: raw.necst.it
May 29-30, 2017. Orlando, Florida USA

The 24th Reconfigurable Architectures Workshop (RAW 2017) will be held in Orlando, Florida USA in May 2017. RAW 2017 is associated with the 31st Annual IEEE International Parallel & Distributed Processing Symposium (IEEE IPDPS 2017) and is sponsored by the IEEE Computer Society and the Technical Committee on Parallel Processing. The workshop is one of the major meetings for researchers to present ideas, results, and on-going research on both theoretical and practical advances in Reconfigurable Computing.

A reconfigurable computing environment is characterized by the ability of underlying hardware architectures or devices to rapidly alter (often on the fly) the functionalities of their components and the interconnection between them to suit the problem at hand. The area has a rich theoretical tradition and wide practical applicability. There are several commercially available reconfigurable platforms (FPGAs and coarse-grained devices) and many modern applications (including embedded systems and HPC) use reconfigurable subsystems. An appropriate mix of theoretical foundations and practical considerations, including algorithms architectures, applications, technologies and tools, is essential to fully exploit the possibilities offered by reconfigurable computing. The Reconfigurable Architectures Workshop aims to provide a forum for creative and productive interaction for researchers and practitioners in the area.


Advance Program (Download as PDF)

May 29, 2017
08.00 - 08.15 Registration
08.15 - 08.30 Opening
08.30 - 09.30 Keynote 1: Heterogeneous Technology Configurable Fabrics: Leveraging Reconfiguration as a Pathway Towards Emerging Devices
Ronald F. DeMara - University of Central Florida, Orlando, FL, USA
Session chair: Ramachandran Vaidyanathan, Louisiana State University, USA
09.30 - 10.00 Short Paper Introduction Session Day 1
Session chair: Ramachandran Vaidyanathan, Louisiana State University, USA
14 Godwin Enemali, Adewale Adetomi and Tughrul Arslan: FAReP: Fragmentation-Aware Replacement Policy for Task Reuse on Reconfigurable FPGAs
11 Sonia Alarcon, Marcin Lukowiak and Tejaswini Ananthanarajana: Power Analysis of HLS-Designed Customized Instruction Set Architectures
25 Tajas Ruschke, Lukas Johannes Jung and Christian Hochberger: A Near Optimal Integrated Solution for Resource Constrained Scheduling, Binding and Routing on CGRAs
13 Adewale Adetomi, Godwin Enemali and Tughrul Arslan: Clock Buffers, Nets, and Trees for On-chip Communication: A Novel Network Access Technique in FPGAs
10.00 - 10.30 Coffee Break and Interactive Session Short Papers Day 1
10.30 - 11.45 Session 1: Architectures for Convolutional Neural Networks and Sliding Window
Session chair: Diana Goehringer, TU Dresden, Germany
9 Marco Bacis, Giuseppe Natale, Emanuele Del Sozzo and Marco Domenico Santambrogio: A Pipelined and Scalable Dataflow Implementation of Convolutional Neural Networks on FPGA
27 Haruyoshi Yonekawa and Hiroki Nakahara: An On-chip Memory Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA
19 Murad Qasaimeh, Phillip Jones and Joseph Zambreno: A Modified Sliding Window Architecture for Efficient BRAM Resource Utilization
11.45 - 12.15 Interactive Session 1
12.15 - 13.15 Lunch
13.15 - 14.55 Session 2: Design and Programming Methods
Session chair: Brian Veale, IBM, USA
8 Gary Grewal, Shawki Areibi, Ziad Abouwaimer, Matthew Westrik and Betty Zhao: Automatic Flow Selection and Quality-of-Result Estimation for FPGA Placement
3 Javier Alejandro Varela, Norbert Wehn, Qian Liang and Songyin Tang: Exploiting Decoupled OpenCL Work-Items with Data Dependencies on FPGAs: A Case Study
10 Luca Stornaiuolo, Alberto Parravicini, Gianluca Durelli and Marco Domenico Santambrogio: Exploiting FPGAs from Higher Level Languages A signal analysis case study
26 Philip Gottschling and Christian Hochberger: ReEP: A Toolset for Generation and Programming of Reconfigurable Datapaths for Event Processing
14.55 - 15.25 Interactive Session 2 and Coffee Break
15.25 - 16.15 Session 3: Acceleration of Curran's Approximation and Elliptic Curve Crypto
Session chair: Juergen Becker, Karlsruhe Institute of Technology, Germany
32 Anna Maria Nestorov, Enrico Reggiani, Marco Domenico Santambrogio, Pavel Burovskiy, Hristina Palikareva and Tobias Becker: A Scalable Dataflow Implementation of Curran’s Approximation Algorithm
28 Rabia Shahid, Ted Winograd and Kris Gaj: A Generic Approach to the Development of Coprocessors for Elliptic Curve Cryptosystems
16.15 – 16.35 Interactive Session 3
16.35 - 17.35 Panel: The Role of Reconfigurable Computing Architectures in the era of Cloud Computing and Data Analytics
Session chair: Marco D. Santambrogio, Politecnico di Milano, Italy
20.00 - 23.00 RAW 2017 social event at Kobe Ichiban Japanese Steakhouse, 8460 Palm Parkway Orlando, FL 32836. (Download Menu)
May 30, 2017
08.30 - 09.30 IPDPS Keynote
09.30 - 10.00 Coffee Break
10.00 - 11.00 Keynote 2: Elastic Dataflow Engines for the Masses
Georgi Gaydadjiev - VP of Dataflow Software Engineering of Maxeler Technologies
Session chair: Marco D. Santambrogio, Politecnico di Milano, Italy
11.00 - 11.25 Short Paper Introduction Session Day 2
Session chair: Marco D. Santambrogio, Politecnico di Milano, Italy
24 Enrico Reggiani, Eleonora D'Arnese, Andrea Purgato and Marco D. Santambrogio: Brain Network acceleration for modeling and mapping of neural interconnections
4 Tripti Jain, Klaus Schneider and Frederik Walk: Function Units in Exposed Datapath Architectures
33 Andres Jacoby and Daniel Llamocca: Dynamic Dual Fixed-Point CORDIC Implementation
23 Emanuele Del Sozzo, Lorenzo Di Tucci and Marco Domenico Santambrogio: A Highly Scalable and Efficient Parallel Design of N-Body Simulation on FPGA
22 Francesca Palumbo, Carlo Sau, Danilo Pani, Paolo Meloni and Luigi Raffo: Real-time Spiking Neural Networks simulation on Swarm Intelligence based digital architecture
11.25 - 11.55 Interactive Session Short Papers Day 2
11.55 - 12.45 Session 4: Acceleration of Biological Signal Processing
Session chair: Emanuele Del Sozzo, Politecnico di Milano, Italy
7 Luca Cerina, Pierandrea Cancian, Giuseppe Franco and Marco Domenico Santambrogio: A Hardware Acceleration for Surface EMG Non-Negative Matrix Factorization
30 Giovanni Pietro Seu, Paolo Meloni, Giuseppe Tuveri, Gian Nicola Angotzi, Luigi Raffo, Luca Berdondini and Alessandro Maccione: On-FPGA Real-time processing of biological signals from high-density MEAs: a design space exploration
12.45 - 14.10 Lunch
14.10 - 15.00 Session 5: Design Methods
Session chair: Lorenzo Di Tucci, Politecnico di Milano, Italy
31 Yosi Ben Asher, Esti Stein and Ramachandran Vaidyanathan: Combining Boolean gates and Branching programs in one model can lead to faster circuits
17 Utsav Agarwal and Ramachandran Vaidyanathan: Efficient Totally-Ordered Subset Generation, with Application in Partial Reconfiguration
15.00 - 15.45 Interactive session 4 + 5 and Coffee Break
15.45 - 16.15 Award Session and Closing Remarks

Topics of interest

Architectures & CAD

  • Algorithmic Techniques and Mapping
  • Emerging Technologies (optical models, 3D Interconnects, devices)
  • Reconfigurable Accelerators
  • Embedded systems and Domain-Specific solutions (Digital Media, Gaming, Automotive applications)
  • FPGA-based MPSoC and Multicore
  • Distributed Systems & Networks
  • Wireless and Mobile Systems
  • Critical issues (Security, Energy efficiency, Fault-Tolerance)

Hot Topics in Reconfigurable Computing

  • Configurable Cloud
  • Heterogeneous Computing in Data Centers
  • Accelerating Data Center Workloads
  • FPGA-based Deep Learning
  • Accelerating Genomic Computations
  • Acceleration of Data Analytics
  • Reconfigurable Computing in the IoT era
  • Organic Computing, Biology-Inspired Solutions
  • Applications in Finance

Runtime & System Management

  • Run-Time Reconfiguration Models and Architectures
  • Autonomic computing systems
  • Operating Systems and High-Level Synthesis
  • High-Level Design Methods (Hardware/Software co-design, Compilers)
  • System Support (Soft processor programming)
  • Runtime Support
  • Reconfiguration Techniques (reusable artifacts)
  • Simulations and Prototyping (performance analysis, verification tools)

Paper Submission

All manuscripts will be reviewed by at least three members of the program committee. Submissions should be a complete manuscript or, in special cases, may be a summary of relevant work. Manuscript for full papers should be not exceed 8 single-spaced, double-column pages using 10-point size font on 8.5X11 inch pages (IEEE conference style) including references, figures and tables. Manuscript for short papers should be not exceed 4 single-space, double-column pages. Papers are to be submitted through EasyChair. Submitted papers should not have appeared in or be under consideration for a different workshop, conference or journal. It is also expected that all accepted papers (regular or short) will be presented at the workshop by one of the authors.


IEEE CS Press will publish the IPDPS symposium and workshop abstracts as a printed volume. Proceedings of the workshops are distributed at the conference and are submitted for inclusion in the IEEE Xplore Digital Library after the conference.

Important Dates

Abstract submission January 11, 2017 February 2, 2017
Submission deadline January 15, 2017 February 5, 2017 (final)
Decision notification March 1, 2017
Camera-Ready papers due March 15, 2017



Workshop Chairs

  • Marco D. Santambrogio, Politecnico di Milano, Italy
  • Ramachandran Vaidyanathan, Louisiana State University, USA

Program Chairs

  • Diana Goehringer, TU Dresden, Germany
  • Donatella Sciuto, Politecnico di Milano, Italy

Program Vice Chairs

  • Dirk Stroobandt, Ghent University, Belgium
  • Francesca Palumbo, Università di Sassari, Italy
  • Ann Gordon-Ross, University of Florida, USA

Steering Committee

  • Juergen Becker, Karlsruhe Institute of Technology, Germany
  • Viktor K. Prasanna, University of Southern California, USA
  • Ramachandran Vaidyanathan, Louisiana State University, USA

Steering Chair:

  • Viktor K. Prasanna, University of Southern California, USA

Publicity Co-Chairs

  • Brian Veale, IBM, USA
  • Ivan Beretta, University of Westminster, UK

Local Arrangements Chair

  • Ronald F. DeMara, University of Central Florida, USA

Program Committee

  • Juergen Becker, Karlsruhe Institute of Technology
  • Ivan Beretta, Imperial College London
  • Michaela Blott, Xilinx
  • Catalin Ciobanu, University of Amsterdam
  • Bruce Cockburn, University of Alberta
  • Jose Coutinho, Imperial College of London
  • Rene Cumplido, INAOE
  • Ken Eguro, Microsoft Research
  • Suhaib Fahmy, University of Warwick
  • Diana Goehringer, TU Dresden, Germany
  • Guy Gogniat, Université de Bretagne Sud
  • Martin Herbordt, Boston University
  • Christian Hochberger, Technische Universitaet Darmstadt
  • Michael Huebner, Ruhr-University Bochum
  • Eddie Hung, Imperial College London
  • Andreas Koch, Technische Universitaet Darmstadt
  • Dirk Koch, University of Manchester
  • Akash Kumar, National University of Singapore
  • Martin Langhammer, Intel
  • Miriam Leeser, Northeastern University
  • Philip Leong, The Chinese University of Hong Kong
  • Gayatri Mehta, University of North Texas
  • Nele Mentens, KU Leuven
  • Antonio Miele, Politecnico di Milano
  • Seda Ogrenci-Memik, Northwestern University
  • Francesca Palumbo, UNISS
  • Dionisios Pnevmatikatos, FORTH-ICS & Technical University of Crete
  • Mario Porrmann, Bielefeld University
  • Viktor Prasanna, University of Southern California
  • Marco Rabozzi, Politecnico di Milano (webmaster)
  • Marco Domenico Santambrogio, Politecnico di Milano
  • Donatella Sciuto, Politecnico di Milano
  • Dimitrios Soudris, National Technical University of Athens
  • Dirk Stroobandt, Ghent University
  • Ramachandran Vaidyanathan, Louisiana State University
  • Wim Vanderbauwhede, University of Glasgow
  • Ana Varbanescu, University of Amsterdam
  • Brian F. Veale, IBM
  • Sara Vinco, Politecnico di Torino
  • Steve Wilton, University of British Columbia


We would like to express our sincere thanks to all those who have contributed to the success of the workshop. In particular, we would like to thank all the members of the program committee and reviewers for their valuable time and effort in the review process, and to provide constructive feedback to the authors. We also acknowledge the support of the IPDPS organizing committee and IEEE Computer Society in producing these proceedings. A special mention has to be done for the EXTRA EU project members. We do really want to thank the members of the EXTRA EU project ("Exploiting eXascale Technology with Reconfigurable Architectures" - http://extrahpc.eu/ - funded from the EU Horizon 2020 research and innovation programme under grant No 671653) for their support in organizing this edition of RAW. Finally, we thank all authors who contributed to this workshop, for submitting their manuscript and sharing their latest research results with the RAW community. We hope that you will find in these proceedings and workshop a valuable platform as well as source of information for your work.