30th Reconfigurable Architectures Workshop
Official website:
May 15th 2023. St. Petersburg, Florida USA

The 30th Reconfigurable Architectures Workshop (RAW 2023) will be held in St. Petersburg, Florida USA in May 2023. RAW 2023 is associated with the 37th Annual IEEE International Parallel & Distributed Processing Symposium (IEEE IPDPS 2023) and is sponsored by the IEEE Computer Society and the Technical Committee on Parallel Processing. The workshop is one of the major meetings for researchers to present ideas, results, and on-going research on both theoretical and practical advances in Reconfigurable Computing.

A reconfigurable computing environment is characterized by the ability of underlying hardware architectures or devices to rapidly alter (often on the fly) the functionalities of their components and the interconnection between them to suit the problem at hand. The area has a rich theoretical tradition and wide practical applicability. There are several commercially available reconfigurable platforms (FPGAs and coarse-grained devices) and many modern applications (including embedded systems and HPC) use reconfigurable subsystems. An appropriate mix of theoretical foundations and practical considerations, including algorithms architectures, applications, technologies and tools, is essential to fully exploit the possibilities offered by reconfigurable computing. The Reconfigurable Architectures Workshop aims to provide a forum for creative and productive interaction for researchers and practitioners in the area.

RAW Program

Reminder about IPDPS 2023 registration: All papers in the workshop must have one author registered at full (non-student) fee. It is assumed that all attendees to the workshop will be registered with IPDPS 2023 to give access to the proceedings and to all live events and recorded sessions of the conference.

May 15th
EDT Time Opening Session
8.30-8.45 Registration
8.45-9.00 Opening Session
Keynote Session 1
9.00-10.00 RAW-Keynote Bobda Christophe: Enabling Transparent Multi-tenancy in FPGA-accelerated Clouds
10.00-10.30 Coffee Break
Session 1: Criptography and Security
10.30-10.55 RAW-03 Benjamin Welte and Joseph Zambreno:An FPGA Implementation of SipHash
10.55-11.20 RAW-05 Can Aknesil, Elena Dubrova, Niklas Lindskog and Håkan Englund:Is Your FPGA Transmitting Secrets: Covert Antennas from Interconnect
11.20-11.25 RAW-08 Quentin Ducasse, Pascal Cotret and Loic Lagadec:JIT Compiler Security through Low-Cost RISC-V Extension
11.25-11.30 RAW-12 Jelle Biesmans, Francesco Regazzoni and Nele Mentens:Application-specific FPGAs: cryptographic agility through customized reconfigurable architectures
11.30-12.00 Poster Session 1
12.00-13.30 Lunch Break
Keynote Session 2
13.30-14.00 RAW-Keynote Viktor Prasanna and Juergen Becker:30 years of RAW
Session 2: Accelerators and Applications
14.00-14.25 RAW-07 D Shaarada Yamini, Mirishkar Ganesh S, Vuppala Anil Kumar and Purini Suresh:Hardware Accelerator for Transformer based End-to-End Automatic Speech Recognition System
14.25-14.50 RAW-06 Mizuki Yasuda, Keisuke Sugiura, Ryuto Kojima and Hiroki Matsutani:An Edge-Server Partitioning Method for 3D LiDAR SLAM on FPGAs
14.50-14.55 RAW-09 Alberto Zeni, Emanuele Del Sozzo, Beatrice Branchini, Lorenzo Di Tucci and Marco Santambrogio:A New Solution For a (Scaff)Old Problem: an FPGA Approach
14.55-15.00 RAW-10 Seongyoung Kang and Sang-Woo Jun:Near-Storage Accelerator for Bulk Graph Ingestion
15.00-15.30 Coffee Break and Poster Session 2
Session 3: Neural Networks and Architectures
15.30-15.55 RAW-01 Ikumi Okubo, Keisuke Sugiura, Hiroki Kawakami and Hiroki Matsutani:A Lightweight Transformer Model using Neural ODE for FPGAs
15.55-16.20 RAW-02 Yuhao Liu, Shubham Rai, Salim Ullah and Akash Kumar:NetPU-M: a Generic Reconfigurable Neural Network Accelerator Architecture for MLPs
16.20-16.45 RAW-04 Sergiu Mosanu, Joshua Fixelle, Mohammad Nazmus Sakib, Kevin Skadron and Mircea Stan:FreezeTime: Towards System Emulation through Architectural Virtualization
16.45-16.50 RAW-11 Filippo Carloni, Leonardo Panseri, Davide Conficconi, Mattia Sironi and Marco Domenico Santambrogio:Enabling Efficient Regular Expression Matching at the Edge through Domain-Specific Architectures
16.50-17.05 Closing Remarks


Enabling Transparent Multi-tenancy in FPGA-accelerated Clouds

Abstract: Cloud computing has become a major trend for delivering services via networks. One of the reasons for its success is that it allows privates and companies to access computing and storage resources on-demand without having to care about the management of the underlying infrastructure. Major IT and Web companies (Microsoft, Oracle, IBM, Amazon, Google, …) have all proposed cloud solutions (AWS, Google Compute Engine, ExaData, …). However, the architectures underneath those cloud services still rely on General Purpose Processors (GPP). Heterogeneous paradigms are well known to offer greater advantages compared to general-purpose computing such as performance improvement and power savings. Because FPGAs outperform GPP and GPUs in several use cases, finding an efficient way to incorporate such computing resources into today’s and tomorrow’s clouds might open a new era for cloud computing. Cloud and data center applications increasingly leverage FPGAs because of their performance/watt benefits and flexibility advantages over traditional processing cores such as CPUs and GPUs. The growing capacity of FPGAs along with increasing demand for hardware acceleration will gradually leads to FPGA multi-tenancy in the cloud, as a means to increase resource utilization. This talk discusses the opportunities but also the challenges that must be overcome to make seamless use of FPGAs in multi-tenant clouds a reality. The issue of resource virtualization, isolation and security as well as applications will de covered.

Speaker Bio: Prof. Bobda is with the University of Florida as Professor of Computer Engineering, leader of the lab smart systems and Associate ECE Chair for Education. Prof. Christophe Bobda is an expert in embedded systems, reconfigurable systems, and system-on-chip with applications in IoT, cybersecurity and is-situ image analysis, particularly hardware/software reconfigurable architectures for acceleration of video processing applications, at the edged and in the cloud. Professor Bobda is Senior Member of the ACM and IEEE. He is also in the program committee of several conferences like DAC, CODES+ISSS, FCCM, FPL and FPT and was ACM ACM Distinguished Speaker from 2016 – 2020. Dr. Bobda has authored more than 200 journal and conference publications in computer architecture, embedded systems, system-on-chip, embedded imaging, robotics and cybersecurity. He received multiple conference awards, including the FCCM Best Short Paper and the SBCCI Test of Time Awards.

Topics of interest

Hot Topics

  • Configurable Cloud
  • Heterogeneous Computing in Data Centers
  • Accelerating Data Center Workloads
  • FPGA-based Deep Learning
  • Accelerating Genomic Computations
  • Accelerating Data Analytics
  • Reconfigurable Computing in the IoT era
  • Organic Computing, Biologically-Inspired Solutions
  • Applications in Finance

Architectures & CAD

  • Algorithmic Techniques and Mapping
  • Emerging Technologies (optical models, 3D Interconnects, devices)
  • Reconfigurable Accelerators
  • Embedded systems and Domain-Specific solutions (Digital Media, Gaming, Automotive applications)
  • FPGA-based MPSoC and Multicore
  • Distributed Systems & Networks
  • Wireless and Mobile Systems
  • Critical issues (Security, Energy efficiency, Fault-Tolerance)

Runtime/System Management

  • RunTime Reconfiguration Models
  • Autonomic computing systems
  • Operating Systems and High-Level Synthesis
  • High-Level Design Methods (Hardware/Software co-design, Compilers)
  • System Support (Soft processor programming)
  • Runtime Support
  • Reconfiguration Techniques (reusable artifacts)
  • Simulations and Prototyping (performance analysis, verification tools)

Paper Submission

All manuscripts will be reviewed by at least three members of the program committee in a single blind review process. Submissions reporting your latest results, exciting developments and, in special cases, summaries of relevant work are sought. Authors are highly encouraged to submit a demo of their work and provide source code/relevant material to reproduce the paper’s results. Manuscripts for full papers should not exceed 8 single-spaced, double-column pages using 10-point font on 8.5 x 11 inch pages (IEEE conference style) including references, figures and tables. Manuscripts for short papers should not exceed 4 single-space, double-column pages. Papers are to be submitted through EasyChair. Submitted papers should not have appeared in or be under consideration for another workshop, conference or journal. It is also expected that all accepted papers (regular or short) will be presented at the workshop by one of the authors.

Instructions For Authors

Please follow the instructions on the IPDPS website for the Camera-Ready paper submission. The paper ID is the number of the authors' submission, the acronym of the workshop is RAW.
In 2023 RAW will celebrate the 30th anniversary, by giving authors the opportunity to submit for evaluation artifacts that accompany their research work. This year this will be a first experiment in this direction. A paper is more than the document itself; it is made o a constellation of artifacts: code, data sets, models, test suites, benchmarks, and others. High-quality artifacts are important as the manuscript itself. Indeed they are needed to reproduce experimental results and build on top of others' research. Because of this context, we are opening a special call for artifacts. Authors of accepted RAW 2023 papers are invited to formally describe supporting materials (code, data, models, workflows, results) to the Artifact Evaluation (AE) process, and for any issue, communicate with the Artifacts Chair.
Note that this submission is voluntary and will not influence the final decision regarding the papers. The goal is to help the authors validate experimental results from their accepted papers by an independent AE Committee in a collaborative way while helping readers find articles with available (i.e., publicly accessible in an archival repository), functional (i.e., consistent, documented, and reusable), and validated (i.e., main results from the paper) artifacts! Each submitted artifact is evaluated by at least two members of the AE committee. During the process, authors and evaluators are allowed to communicate anonymously with each other to overcome technical difficulties. Ideally, we hope to see all submitted artifacts successfully pass the artifact evaluation. More details on the AE process will follow.


IEEE CS Press will publish the IPDPS symposium and workshop abstracts as a printed volume. Proceedings of the workshops are distributed at the conference and are submitted for inclusion in the IEEE Xplore Digital Library after the conference.

Important Dates

Submission deadline: January 23, 2023 February 10, 2023
Decision notification: February 14, 2023 March 6, 2023
Camera-Ready papers due: February 28, 2023 March 15, 2023


Workshop Chair

Program Chair

  • Lana Josipović, ETH Zurich, Switzerland

Steering Committee

  • Juergen Becker, Karlsruhe Institute of Technology, Germany
  • Viktor K. Prasanna, University of Southern California, USA
  • Ramachandran Vaidyanathan, Louisiana State University, USA

Steering Chair

  • Viktor K. Prasanna, University of Southern California, USA

Artifacts Chair

  • Davide Conficconi, Politecnico di Milano, Italy

Publicity Co-Chairs

  • Brian Veale, IBM, USA
  • Dirk Stroobandt, Ghent University, Belgium
  • Yukinori Sato, Toyohashi University of Technology, Japan


  • Francesco Peverelli, Politecnico di Milano, Italy

Program Committee

  • Antonio Miele, Politecnico di Milano
  • Bruce Cockburn, University of Alberta
  • Catalin Bogdan Ciobanu, University of Amsterdam
  • Christian Hochberger, TU Darmstadt
  • Davide Conficconi, Politecnico di Milano
  • Dennis Gnad, Karlsruhe Institute of Technology
  • Diana Goehringer, TU Dresden
  • Dimitrios Soudris, National Technical University of Athens
  • Dionisios Pnevmatikatos, National Technical University of Athens
  • Emanuele Del Sozzo, RIKEN Center for Computational Science
  • Francesc Fons, Huawei Technologies
  • Francesco Peverelli, Politecnico di Milano
  • Jo Vliegen, Katholieke Universiteit Leuven
  • John Wickerson, Imperial College London
  • Jürgen Becker, Karlsruhe Institute of Technology
  • Lana Josipovic, ETH Zurich
  • Lorenzo Di Tucci, Huxelerate SRL
  • Marco Domenico Santambrogio, Politecnico di Milano
  • Mario Porrmann, Osnabrueck University
  • Martin Herbordt, Boston University
  • Martin Langhammer, Intel
  • Michael Huebner, Brandenburg University of Technology Cottbus
  • Oliver Sinnen, University of Auckland
  • Qiang Liu, Tianjin University
  • Ramachandran Vaidyanathan, Louisiana State University
  • Shaojun Wang, Harbin Institute of Technology
  • Tomohiro Ueno, RIKEN Center for Computational Science
  • Viktor Prasanna, University of Southern California
  • Yasunori Osana, University of the Ryukyus
  • Yuichiro, Nagasaki University
  • Yukinori Sato, Toyohashi University of Technology

Artifacts Evaluation Committee

  • Filippo Carloni, Politecnico di Milano, Italy
  • Francesco Ratto, University of Cagliari, Italy
  • Murat Isik, Drexel University, USA