The 30th Reconfigurable Architectures Workshop (RAW 2023) will be held in St. Petersburg, Florida USA in May 2023. RAW 2023 is associated with the 37th Annual IEEE International Parallel & Distributed Processing Symposium (IEEE IPDPS 2023) and is sponsored by the IEEE Computer Society and the Technical Committee on Parallel Processing. The workshop is one of the major meetings for researchers to present ideas, results, and on-going research on both theoretical and practical advances in Reconfigurable Computing.
A reconfigurable computing environment is characterized by the ability of underlying hardware architectures or devices to rapidly alter (often on the fly) the functionalities of their components and the interconnection between them to suit the problem at hand. The area has a rich theoretical tradition and wide practical applicability. There are several commercially available reconfigurable platforms (FPGAs and coarse-grained devices) and many modern applications (including embedded systems and HPC) use reconfigurable subsystems. An appropriate mix of theoretical foundations and practical considerations, including algorithms architectures, applications, technologies and tools, is essential to fully exploit the possibilities offered by reconfigurable computing. The Reconfigurable Architectures Workshop aims to provide a forum for creative and productive interaction for researchers and practitioners in the area.
Reminder about IPDPS 2023 registration: All papers in the workshop must have one author registered at full (non-student) fee. It is assumed that all attendees to the workshop will be registered with IPDPS 2023 to give access to the proceedings and to all live events and recorded sessions of the conference.
|EDT Time||Opening Session|
|Keynote Session 1|
|Session 1: Criptography and Security|
|10.30-10.55||RAW-03||Benjamin Welte and Joseph Zambreno:An FPGA Implementation of SipHash|
|10.55-11.20||RAW-05||Can Aknesil, Elena Dubrova, Niklas Lindskog and Håkan Englund:Is Your FPGA Transmitting Secrets: Covert Antennas from Interconnect|
|11.20-11.25||RAW-08||Quentin Ducasse, Pascal Cotret and Loic Lagadec:JIT Compiler Security through Low-Cost RISC-V Extension|
|11.25-11.30||RAW-12||Jelle Biesmans, Francesco Regazzoni and Nele Mentens:Application-specific FPGAs: cryptographic agility through customized reconfigurable architectures|
|11.30-12.00||Poster Session 1|
|Keynote Session 2|
|13.30-14.00||RAW-Keynote||Viktor Prasanna and Juergen Becker:30 years of RAW|
|Session 2: Accelerators and Applications|
|14.00-14.25||RAW-07||D Shaarada Yamini, Mirishkar Ganesh S, Vuppala Anil Kumar and Purini Suresh:Hardware Accelerator for Transformer based End-to-End Automatic Speech Recognition System|
|14.25-14.50||RAW-06||Mizuki Yasuda, Keisuke Sugiura, Ryuto Kojima and Hiroki Matsutani:An Edge-Server Partitioning Method for 3D LiDAR SLAM on FPGAs|
|14.50-14.55||RAW-09||Alberto Zeni, Emanuele Del Sozzo, Beatrice Branchini, Lorenzo Di Tucci and Marco Santambrogio:A New Solution For a (Scaff)Old Problem: an FPGA Approach|
|14.55-15.00||RAW-10||Seongyoung Kang and Sang-Woo Jun:Near-Storage Accelerator for Bulk Graph Ingestion|
|15.00-15.30||Coffee Break and Poster Session 2|
|Session 3: Neural Networks and Architectures|
|15.30-15.55||RAW-01||Ikumi Okubo, Keisuke Sugiura, Hiroki Kawakami and Hiroki Matsutani:A Lightweight Transformer Model using Neural ODE for FPGAs|
|15.55-16.20||RAW-02||Yuhao Liu, Shubham Rai, Salim Ullah and Akash Kumar:NetPU-M: a Generic Reconfigurable Neural Network Accelerator Architecture for MLPs|
|16.20-16.45||RAW-04||Sergiu Mosanu, Joshua Fixelle, Mohammad Nazmus Sakib, Kevin Skadron and Mircea Stan:FreezeTime: Towards System Emulation through Architectural Virtualization|
|16.45-16.50||RAW-11||Filippo Carloni, Leonardo Panseri, Davide Conficconi, Mattia Sironi and Marco Domenico Santambrogio:Enabling Efficient Regular Expression Matching at the Edge through Domain-Specific Architectures|