The 29th Reconfigurable Architectures Workshop (RAW 2022) will be held in Lyon, France in May 2022. RAW 2022 is associated with the 36th Annual IEEE International Parallel & Distributed Processing Symposium (IEEE IPDPS 2022) and is sponsored by the IEEE Computer Society and the Technical Committee on Parallel Processing. The workshop is one of the major meetings for researchers to present ideas, results, and on-going research on both theoretical and practical advances in Reconfigurable Computing.
A reconfigurable computing environment is characterized by the ability of underlying hardware architectures or devices to rapidly alter (often on the fly) the functionalities of their components and the interconnection between them to suit the problem at hand. The area has a rich theoretical tradition and wide practical applicability. There are several commercially available reconfigurable platforms (FPGAs and coarse-grained devices) and many modern applications (including embedded systems and HPC) use reconfigurable subsystems. An appropriate mix of theoretical foundations and practical considerations, including algorithms architectures, applications, technologies and tools, is essential to fully exploit the possibilities offered by reconfigurable computing. The Reconfigurable Architectures Workshop aims to provide a forum for creative and productive interaction for researchers and practitioners in the area.
Reminder about IPDPS 2022 registration: All papers in the workshop must have one author registered at full (non-student) fee. It is assumed that all attendees to the workshop will be registered with IPDPS 2022 to give access to the proceedings and to all live events and recorded sessions of the conference.
|17.00 CEST||Opening of the conferenece|
|17.15 CEST||RAW-Keynote||Stephen Neuendorffer:Programming AIEngine Devices with MLIR|
|Session 1: Machine Learning and Design Automation|
|18.15 CEST||RAW-05||Daniele Paletti, Francesco Peverelli, Davide Conficconi:Online Learning RTL Synthesis for Automated Design Space Exploration|
|18.20 CEST||RAW-14||Dana Diaconu, Lucian Petrica, Michaela Blott and Miriam Leeser:Machine Learning Aided Hardware Resource Estimation for FPGA DNN Implementations|
|18.25 CEST||RAW-18||Lester Kalms, Tim Häring and Diana Goehringer:DECISION: Distributing OpenVX Applications on CPUs, GPUs and FPGAs using OpenCL|
|18.30 CEST||RAW-11||Jonas Ney, Bilal Hammoud and Norbert Wehn:A Hybrid Approach combining ANN-based and Conventional Demapping in Communication for Efficient FPGA-Implementation|
|18.35 CEST||RAW-16||Pascal Jungblut and Dieter Kranzlmüller:Optimal Schedules for High-Level Programming Environments on FPGAs with Constraint Programming|
|18.40 CEST||RAW-17||Seung-Hun Chung and Tarek Abdelrahman:Optimization of Compiler-Generated OpenCL CNN Kernels and Runtime for FPGAs|
|18.45 CEST||Q&A Sesssion|
|17.00 CEST||RAW-Keynote||Gustavo Alonso:Using FPGAs in datacenters and the cloud|
|Session 2: Accelerators and Applications|
|18.00 CEST||RAW-04||Raffaele Berzoini, Eleonora D'Arnese, Davide Conficconi:On How to Push Efficient Medical Semantic Segmentation to the Edge: the SENECA approach|
|18.05 CEST||RAW-07||Lukas Weber, Johannes Wirth, Lukas Sommer and Andreas Koch:Exploiting High-Bandwidth Memory for FPGA-Acceleration of Inference on Sum-Product Networks|
|18.10 CEST||RAW-23||Lennart Clausing and Marco Platzner:ReconOS64: A Hardware Operating System for Modern Platform FPGAs with 64-Bit Support|
|18.15 CEST||RAW-02||Tze Hon Tan, Chia Yee Ooi and Muhammad Nadzir Marsono:An FPGA-based IP Core Subscription-Oriented Fog Computing Platform|
|18.20 CEST||RAW-13||Mingyuan Yang, Yemeng Zhang, Bohan Yang, Hanning Wang, Shouyi Yin, Shaojun Wei and Leibo Liu:A SHA-512 Hardware Implementation Based on Block RAM Storage Structure|
|18.25 CEST||RAW-24||Beatrice Branchini, Sofia Breschi, Alberto Zeni and Marco Santambrogio:Fast Genome Analysis Leveraging Exact String Matching|
|18.30 CEST||Q&A Sesssion|
|19.00 CEST||Closing remarks|