Lyon

29th Reconfigurable Architectures Workshop
Official website: raw.necst.it
May 30th-31st 2022. Lyon, France

The 29th Reconfigurable Architectures Workshop (RAW 2022) will be held in Lyon, France in May 2022. RAW 2022 is associated with the 36th Annual IEEE International Parallel & Distributed Processing Symposium (IEEE IPDPS 2022) and is sponsored by the IEEE Computer Society and the Technical Committee on Parallel Processing. The workshop is one of the major meetings for researchers to present ideas, results, and on-going research on both theoretical and practical advances in Reconfigurable Computing.

A reconfigurable computing environment is characterized by the ability of underlying hardware architectures or devices to rapidly alter (often on the fly) the functionalities of their components and the interconnection between them to suit the problem at hand. The area has a rich theoretical tradition and wide practical applicability. There are several commercially available reconfigurable platforms (FPGAs and coarse-grained devices) and many modern applications (including embedded systems and HPC) use reconfigurable subsystems. An appropriate mix of theoretical foundations and practical considerations, including algorithms architectures, applications, technologies and tools, is essential to fully exploit the possibilities offered by reconfigurable computing. The Reconfigurable Architectures Workshop aims to provide a forum for creative and productive interaction for researchers and practitioners in the area.

Virtual RAW Program

Reminder about IPDPS 2022 registration: All papers in the workshop must have one author registered at full (non-student) fee. It is assumed that all attendees to the workshop will be registered with IPDPS 2022 to give access to the proceedings and to all live events and recorded sessions of the conference.

May 30th
Opening Session
17.00 CESTOpening of the conferenece
Keynote Session
17.15 CESTRAW-KeynoteStephen Neuendorffer:Programming AIEngine Devices with MLIR
Session 1: Machine Learning and Design Automation
18.15 CESTRAW-05Daniele Paletti, Francesco Peverelli, Davide Conficconi:Online Learning RTL Synthesis for Automated Design Space Exploration
18.20 CESTRAW-14Dana Diaconu, Lucian Petrica, Michaela Blott and Miriam Leeser:Machine Learning Aided Hardware Resource Estimation for FPGA DNN Implementations
18.25 CESTRAW-18Lester Kalms, Tim Häring and Diana Goehringer:DECISION: Distributing OpenVX Applications on CPUs, GPUs and FPGAs using OpenCL
18.30 CESTRAW-11Jonas Ney, Bilal Hammoud and Norbert Wehn:A Hybrid Approach combining ANN-based and Conventional Demapping in Communication for Efficient FPGA-Implementation
18.35 CESTRAW-16Pascal Jungblut and Dieter Kranzlmüller:Optimal Schedules for High-Level Programming Environments on FPGAs with Constraint Programming
18.40 CESTRAW-17Seung-Hun Chung and Tarek Abdelrahman:Optimization of Compiler-Generated OpenCL CNN Kernels and Runtime for FPGAs
18.45 CESTQ&A Sesssion
May 31st
Keynote Session
17.00 CESTRAW-KeynoteGustavo Alonso:Using FPGAs in datacenters and the cloud
Session 2: Accelerators and Applications
18.00 CESTRAW-04Raffaele Berzoini, Eleonora D'Arnese, Davide Conficconi:On How to Push Efficient Medical Semantic Segmentation to the Edge: the SENECA approach
18.05 CESTRAW-07Lukas Weber, Johannes Wirth, Lukas Sommer and Andreas Koch:Exploiting High-Bandwidth Memory for FPGA-Acceleration of Inference on Sum-Product Networks
18.10 CESTRAW-23Lennart Clausing and Marco Platzner:ReconOS64: A Hardware Operating System for Modern Platform FPGAs with 64-Bit Support
18.15 CESTRAW-02Tze Hon Tan, Chia Yee Ooi and Muhammad Nadzir Marsono:An FPGA-based IP Core Subscription-Oriented Fog Computing Platform
18.20 CESTRAW-13Mingyuan Yang, Yemeng Zhang, Bohan Yang, Hanning Wang, Shouyi Yin, Shaojun Wei and Leibo Liu:A SHA-512 Hardware Implementation Based on Block RAM Storage Structure
18.25 CESTRAW-24Beatrice Branchini, Sofia Breschi, Alberto Zeni and Marco Santambrogio:Fast Genome Analysis Leveraging Exact String Matching
18.30 CESTQ&A Sesssion
19.00 CESTClosing remarks

Keynotes

Using FPGAs in datacenters and the cloud

Abstract: Several trends in the IT industry are driving an increasing specialization of the hardware layers. On the one hand, demanding workloads, large data volumes, diversity in data types, etc. are all factors contributing to make general purpose computing too inefficient. On the other hand, cloud computing and its economies of scale allow vendors to invest on specialized hardware for particular tasks that otherwise would be too expensive or consume resources needed elsewhere. In this talk I will discuss the shift towards hardware acceleration and show with several examples from industry and from research the large role that FPGAs could play.

Speaker Bio: Gustavo Alonso is a professor in the Department of Computer Science of ETH Zurich where he is a member of the Systems Group. His research interests include data management, distributed systems, cloud computing, and hardware acceleration. Gustavo is an ACM Fellow and an IEEE Fellow as well as a Distinguished Alumnus of the Department of Computer Science of UC Santa Barbara.


Programming AIEngine Devices with MLIR

Abstract: With the slowing of CMOS technology scaling trends and the continued growth of compute requirements for applications like 5G wireless and machine learning, there has been a widespread emphasis on new accelerator architectures emphasizing heterogeneity. However, programming heterogeneous devices can be challenging, requiring heterogenous design tools supporting multiple levels of abstraction. This talk will present our work to develop open design tools for Xilinx Versal devices with AIEngine processors based on MLIR, a new compiler infrastructure which directly supports multiple levels of abstraction.

Speaker Bio: Stephen Neuendorffer is a Distinguished Engineer in the Xilinx Research Labs working on various aspects of system design for FPGAs. Previously, he was product architect of Xilinx Vivado HLS and co-authored a widely used textbook on HLS design for FPGAs. He received B.S. degrees in Electrical Engineering and Computer Science from the University of Maryland, College Park in 1998. He graduated with University Honors, Departmental Honors in Electrical Engineering, and was named the Outstanding Graduate in the Department of Computer Science. He received the Ph.D. degree from the University of California, Berkeley, in 2003, after being one of the key architects of Ptolemy II.

Topics of interest

Hot Topics

  • Configurable Cloud
  • Heterogeneous Computing in Data Centers
  • Accelerating Data Center Workloads
  • FPGA-based Deep Learning
  • Accelerating Genomic Computations
  • Accelerating Data Analytics
  • Reconfigurable Computing in the IoT era
  • Organic Computing, Biologically-Inspired Solutions
  • Applications in Finance

Architectures & CAD

  • Algorithmic Techniques and Mapping
  • Emerging Technologies (optical models, 3D Interconnects, devices)
  • Reconfigurable Accelerators
  • Embedded systems and Domain-Specific solutions (Digital Media, Gaming, Automotive applications)
  • FPGA-based MPSoC and Multicore
  • Distributed Systems & Networks
  • Wireless and Mobile Systems
  • Critical issues (Security, Energy efficiency, Fault-Tolerance)

Runtime/System Management

  • RunTime Reconfiguration Models
  • Autonomic computing systems
  • Operating Systems and High-Level Synthesis
  • High-Level Design Methods (Hardware/Software co-design, Compilers)
  • System Support (Soft processor programming)
  • Runtime Support
  • Reconfiguration Techniques (reusable artifacts)
  • Simulations and Prototyping (performance analysis, verification tools)

Paper Submission

All manuscripts will be reviewed by at least three members of the program committee in a single blind review process. Submissions reporting your latest results, exciting developments and, in special cases, summaries of relevant work are sought. Authors are highly encouraged to submit a demo of their work and provide source code/relevant material to reproduce the paper’s results. Manuscripts for full papers should not exceed 8 single-spaced, double-column pages using 10-point font on 8.5 x 11 inch pages (IEEE conference style) including references, figures and tables. Manuscripts for short papers should not exceed 4 single-space, double-column pages. Papers are to be submitted through EasyChair. Submitted papers should not have appeared in or be under consideration for another workshop, conference or journal. It is also expected that all accepted papers (regular or short) will be presented at the workshop by one of the authors.

Instructions For Authors

Please follow the instructions on the IPDPS website for the Camera-Ready paper submission. The paper ID is the number of the authors' submission, the acronym of the workshop is RAW.

Publication

IEEE CS Press will publish the IPDPS symposium and workshop abstracts as a printed volume. Proceedings of the workshops are distributed at the conference and are submitted for inclusion in the IEEE Xplore Digital Library after the conference.

Important Dates

Submission deadline January 21, 2022 February 11, 2022
Decision notification February 28, 2022
Camera-Ready papers due March 11, 2022 March 21, 2022

Organization

Workshop Chair

Program Chair

  • Lana Josipović, ETH Zurich, Switzerland

Steering Committee

  • Juergen Becker, Karlsruhe Institute of Technology, Germany
  • Viktor K. Prasanna, University of Southern California, USA
  • Ramachandran Vaidyanathan, Louisiana State University, USA

Steering Chair

  • Viktor K. Prasanna, University of Southern California, USA

Publicity Co-Chairs

  • Brian Veale, IBM, USA
  • Dirk Stroobandt, Ghent University, Belgium
  • Yukinori Sato, Toyohashi University of Technology, Japan

Webmaster

  • Francesco Peverelli, Politecnico di Milano, Italy

Program Committee

  • Antonio Rosario Miele, Politecnico di Milano
  • Alexander Kroh, UNSW Sydney
  • Brian F. Veale, IBM
  • Bruce Cockburn, University of Alberta
  • Catalin Bogdan Ciobanu, University of Amsterdam
  • Christian Hochberger, Technische Universitaet Darmstadt
  • Davide Conficconi, Politecnico di Milano
  • Dennis Gnad, Karlsruher, Institut für Technologie
  • Diana Goehringer, TU Dresden
  • Dimitrios Soudris, National Technical University of Athens
  • Dionisios Pnevmatikatos, FORTH-ICS & Technical University of Crete
  • Dirk Koch, University of Manchester
  • Eddie Hung, Imperial College London
  • Emanuele Del Sozzo, Politecnico di Milano
  • Fernanda Lima Kastensmidt, UFRGS
  • Francesc Fons, Huawei Technologies
  • Gayatri Mehta, University of North Texas
  • Guy Gogniat, Université de Bretagne Sud
  • Hayden Kwok-Hay So, University of Hong Kong
  • John Wickerson, Imperial College London
  • Jürgen Becker, Karlsruher, Institut für Technologie
  • Lingli Wang, Fudan University
  • Lorenzo Di Tucci, Huxelerate
  • Mario Porrmann, Osnabrück University
  • Martin Herbordt, Boston University
  • Martin Langhammer, Intel
  • Michael Huebner, Brandenburg University of Technology
  • Miriam Leeser, Northeastern University
  • Nele Mentens, KU Leuven
  • Oliver Sinnen, University of Auckland
  • Qiang Liu, Tianjin University
  • Ramachandran Vaidyanathan, Louisiana State University
  • Sara Vinco, Politecnico di Torino
  • Seda Ogrenci-Memik, Northwestern University
  • Shaojun Wang, Harbin Institute of Technology
  • Viktor Prasanna, University of Southern California
  • Yasunori Osana, University of the Ryukyus
  • Yuichiro Shibata, Nagasali University
  • Yukinori Sato, Toyohashi University of Technology