StPetersburg

31st Reconfigurable Architectures Workshop
Official website: raw.necst.it
May 27th-28th 2024. San Francisco, California, USA

The 31st Reconfigurable Architectures Workshop (RAW 2024) will be held in San Francisco, California USA on May 27th and 28th 2024. RAW 2024 is associated with the 38th Annual IEEE International Parallel & Distributed Processing Symposium (IEEE IPDPS 2024) and is sponsored by the IEEE Computer Society and the Technical Committee on Parallel Processing. The workshop is one of the major meetings for researchers to present ideas, results, and on-going research on both theoretical and practical advances in Reconfigurable Computing.

A reconfigurable computing environment is characterized by the ability of underlying hardware architectures or devices to rapidly alter (often on the fly) the functionalities of their components and the interconnection between them to suit the problem at hand. The area has a rich theoretical tradition and wide practical applicability. There are several commercially available reconfigurable platforms (FPGAs and coarse-grained devices) and many modern applications (including embedded systems and HPC) use reconfigurable subsystems. An appropriate mix of theoretical foundations and practical considerations, including algorithms architectures, applications, technologies and tools, is essential to fully exploit the possibilities offered by reconfigurable computing. The Reconfigurable Architectures Workshop aims to provide a forum for creative and productive interaction for researchers and practitioners in the area.

RAW Program

Indicates best paper candidate
Room for all sessions on May 27th: Grand Ballroom B
Room for all sessions (except keynote) on May 28th: Grand Ballroom C
May 27th
PDT Opening Session
8.30-8.45 Registration
8.45-9.00 Opening Prof. Zhenman Fang, Simon Fraser University
Prof. Marco Domenico Santambrogio, Politecnico di Milano
Keynote Session 1
Chair: Prof. Zhenman Fang, Simon Fraser University
9.00-10.00 RAW-Keynote Prof. Deming Chen, University of Illinois at Urbana-Champaign: The Next Wave of HLS: Fully Automated PyTorch-to-Accelerator Design Flow
10.00-10.30 Coffee Break
Session 1: Machine Learning and Quantum Computing
Chair: Prof. Hayden Kwok-Hay So, University of Hong Kong
10.30-10.55 Full Yufei Mao, Yu Li, Marc Rothmann, Yi Zhang, Roland Weiss, Mario Porrmann:FPGA Acceleration of DL-Based Real-Time DC Series Arc Fault Detection
10.55-11.20 Full Federico Valentino, Beatrice Branchini, Davide Conficconi, Donatella Sciuto, Marco Santambrogio:An Accurate Union Find Decoder for Quantum Error Correction on the Toric Code
11.20-11.30 Short Marco Venere, Valentino Guerrini, Beatrice Branchini, Davide Conficconi, Donatella Sciuto, Marco Santambrogio:Towards the Acceleration of the Sparse Blossom Algorithm for Quantum Error Correction
11.30-11.40 Short Erik DHollander, Ewout Danneels, Karel-Brecht Decorte, Senne Loobuyck, Arne Vanheule, Ian Van Kets, Dirk Stroobandt:Exploring Large Language Models for Verilog Hardware Design Generation
11.40-13.40 Poster Session with Luncheon
Chair: Dr. Andrew Schmidt, AMD
Special Session: Reconfigurable Computing Advances in Europe
Chair: Prof. Marco Domenico Santambrogio, Politecnico di Milano
13.40-13.55 Prof. Wayne Luk, Imperial College London:Auto-Generating Diverse Heterogeneous Designs
13.55-14.10 Prof. Dirk Stroobandt, Ghent University:Reconfigurable Computing: Quo Vadis?
14.10-14.25 Prof. Diana Göhringer, TU Dresden:Self-aware Reliable and Reconfigurable Computing Systems - An Overview
14.25-14.40 Prof. Stefania Perri, University of Calabria:Digital In-Memory Computing to Accelerate Deep Learning Inference on the Edge
14.40-15.30 Panel Discussion
15.30-16.00 Coffee Break
Session 2: Accelerators and Applications
Chair: Dr. Guido Walter Di Donato, Politecnico di Milano
16.00-16.25 Full Samuel Collinson, Allan Bai, Oliver Sinnen:A Fast Scalable Hardware Priority Queue and Optimizations for Multi-Pushes
16.25-16.50 Full Claudio Rubattu, Antonio Ledda, Francesco Ratto, Chaitanya Jugade, Dip Goswami, Francesca Palumbo:FPGA-based Implementation for Industrial Motion Control System
16.50-17.15 Full Kazuki Sunaga, Keisuke Sugiura, Hiroki Matsutani:An FPGA-Based Accelerator for Graph Embedding using Sequential Training Algorithm
18.00-19.30 IPDPS - TCPP Welcome Reception
May 28th
PDT Keynote Session 2 (Shared with IPDPS), Grand Ballroom
8.30-9.30 RAW-Keynote Dr. Franck Cappello, Argonne National Laboratory: TBD
9.30-10.00 Coffee Break
Session 3: Architecture and Toolflow
Chair: Prof. Davide Conficconi, Politecnico di Milano
10.00-10.25 Full Carsten Heinz, Torben Kalkhof, Yannick Lavan, Andreas Koch:TaPaSCo-AIE: An Open-Source Framework for Streaming-based Heterogeneous Acceleration using AMD AI Engines
10.25-10.50 Full Anna Drewes, Vitalii Burtsev, Bala Gurumurthy, Martin Wilhelm, David Broneske, Gunter Saake, Thilo Pionteck, Otto-von-Guericke University Magdeburg:An Architectural Template for FPGA Overlays Targeting Data Flow Applications
10.50-11.15 Full Sahan Bandara, Ahmed Sanaullah, Zaid Tahir, Ulrich Drepper, Martin Herbordt:Performance Evaluation of VirtIO Device Drivers for Host-FPGA PCIe Communication
11.15-11.40 Invited Dr. Andrew Schmidt, AMD:Riallto: An Open-Source Exploratory Framework for Ryzen AI™
11.40-13.30 Lunch Break
Special Session: Reconfigurable Computing Advances in Asia
Chair: Prof. Zhenman Fang, Simon Fraser University
13.30-13.45 Prof. Masato Motomura, Tokyo Institute of Technology:Reconfigurable AI Processing for Embedded Systems
13.45-14.00 Dr. Kentaro Sano, RIKEN:Reconfigurable Architectures for High-Performance Computing
14.00-14.15 Prof. Wei Zhang, Hong Kong University of Science and Technology:Efficient Cross-layer Design Flow for Multi-die FPGA
14.15-14.30 Prof. Hayden Kwok-Hay So, University of Hong Kong:Practical Reconfigurable Computing for Next-Generation Edge Applications
14.30-15.20 Panel Discussion
15.20-15.30 Closing and Award Cerimony

Keynotes

Monday Keynote: The Next Wave of HLS: Fully Automated PyTorch-to-Accelerator Design Flow

Abstract: In this talk, we introduce a new design flow, ScaleHLS, that established a new High-Level Synthesis (HLS) solution translating AI models described in PyTorch to customized AI accelerators automatically. By adopting PyTorch as input for AI designs (instead of traditional C/C++ for HLS), the lines of code and design simulation time can be reduced by about 10× and 100×, respectively. Meanwhile, despite being fully automated and able to handle various applications, this new flow achieves a 1.29x higher throughput over DNNBuilder, a state-of-the-art RTL-based neural network accelerator on FPGAs. Such AI model-to-RTL flows pave the way for a new wave of HLS that could drive the high-productivity designs of AI circuits with high density, high-energy efficiency, low cost, and short design cycle. And such high-level model-to-RTL flows can be expanded to other non-AI domains. However, we are also facing existing and new challenges for such HLS solutions, such as ensuring the correctness of the high-level design, accommodating accurate low-level timing/energy information, handling the complexity of 3D circuits and/or chiplet-based design flows, and achieving all these in a highly scalable manner.

Speaker Bio: Deming Chen is the Abel Bliss Professor of the Grainger College of Engineering at University of Illinois at Urbana-Champaign (UIUC). His current research interests include reconfigurable and heterogenous computing, system-level design methodologies, machine learning and acceleration, hybrid cloud, and hardware security. He has published more than 270 research papers, received 10 Best Paper Awards and one ACM/SIGDA TCFPGA Hall-of-Fame Paper Award, and given more than 150 invited talks. His research has generated high impact, with open-sourced solutions widely adopted by both academia and industry (e.g., FCUDA, DNNBuilder, CSRNet, SkyNet, ScaleHLS). He is an IEEE Fellow, an ACM Distinguished Speaker, and the Editor-in-Chief of ACM Transactions on Reconfigurable Technology and Systems (TRETS). He is the Director of the AMD-Xilinx Center of Excellence and the Hybrid-Cloud Thrust Co-Lead of the IBM-Illinois Discovery Accelerator Institute at UIUC. He has been involved in several startup companies, such as AutoESL and Inspirit IoT. He received his Ph.D. from the Computer Science Department of UCLA in 2005.

Tuesday Keynote: shared with IPDPS

Talk Info: More information will be posted soon on the IPDPS website
Speaker: Franck Cappello, Argonne National Laboratory

Accepted Posters

  • Short Paper: Towards the Acceleration of the Sparse Blossom Algorithm for Quantum Error Correction, Marco Venere, Valentino Guerrini, Beatrice Branchini, Davide Conficconi, Donatella Sciuto, Marco Santambrogio, Politecnico di Milano
  • Short Paper: Exploring Large Language Models for Verilog Hardware Design Generation, Erik DHollander, Ewout Danneels, Karel-Brecht Decorte, Senne Loobuyck, Arne Vanheule, Ian Van Kets, Dirk Stroobandt, Ghent University
  • Balancing Intra-Die and Inter-Die Placement Optimization in 2.5D FPGA Architectures, Raveena Raikar, Dirk Stroobandt, Ghent university
  • ML-based Real-Time Control at the Edge: An Approach Using hls4ml, Rui Shi, Seda Ogrenci, Northwestern University; Jeremy Arnold, Jose Berlioz, Pierrick Hanlet, Kyle Hazelwood, Aisha Ibrahim, Fermi National Accelerator Laboratory; Han Liu, Northwestern University; Vladimir Nagaslaev, Aakaash Narayanan, Dennis Nicklaus, Jovan Mitrevski, Gauri Pradhan, Andrea Saewert, Brian Schupbach, Kiyomi Seiya, Fermi National Accelerator Laboratory; Mattson Thieme, Northwestern University; Randy Thurman-Keup, Nhan Tran, Fermi National Accelerator Laboratory
  • ConvMap: Boosting Convolution Throughput on FPGAs with Efficient Resource Mapping, Shubhayu Das, Nanditha Rao, IIIT Bangalore; Sharad Sinha, IIT Goa
  • A Reconfigurable Architecture of a Scalable, Ultrafast, Ultrasound, Delay-and-Sum Beamformer, Vasilis Kypriotis, National Technical University of Athens; George Smaragdos, Pieter Kruizinga, Erasmus Medical Center, Rotterdam; Dimitrios Soudris, National Technical University of Athens; Christos Strydis, Delft University of Technology and Erasmus Medical Center, Rotterdam
  • Accelerating TinyML Inference on Microcontrollers through Approximate Kernels, Giorgos Armeniakos, Georgios Mentzos, Dimitrios Soudris, National and Technical University of Athens
  • HPC Systems with Reconfigurable Optical Networks: Performance and Energy Consumption Exploration, Xianwei Cheng, Che-Yu Liu, University of California, Davis; Roberto Proietti, Politecnico di Torino; S. J. Ben Yoo, University of California, Davis
  • Scalable Dual-Instruction Multiple-Data Processing on an Efficient Systolic-Array Architecture, Yuxi Tan, University of Tsukuba; Riadh Ben Abdelhamid, Heidelberg University; BingJie Guo, Qixiang Gao, Masaru Nishimura, University of Tsukuba; Yoshiki Yamaguchi, University of Tsukuba, Kumamoto University
  • POCA: a PYNQ Offloaded Cryptographic Accelerator on Embedded FPGA-based Systems, Roberto Alessandro Bertolini, Filippo Carloni, Davide Conficconi, Marco Domenico Santambrogio, Politecnico di Milano
  • Network Adapter for Secure Networks-on-Chip, Julian Haase, Nico Volkens, Diana Göhringer, TU Dresden
  • Multi-core Multi-rule VeBPF Firewall for Secure FPGA IoT Device Deployments, Zaid Tahir, Martin Herbordt, Boston University
  • Quantum and EDA: Towards The Joint Development Of Two Pillars Of Computer Science, Marco Venere and Marco Domenico Santambrogio, Politecnico di Milano
  • Leveraging Heterogeneous Architectures for High-Performance Genomics Analyses, Beatrice Branchini and Marco Domenico Santambrogio, Politecnico di Milano
  • MARCH: Multi-staging Array Compiler for High-Level Synthesis, Francesco Peverelli and Marco Santambrogio, Politecnico di Milano
  • YoseUe: Efficient Inference of Large Random Forests on embedded devices, Alessandro Verosimile and Marco D. Santambrogio, Politecnico di Milano
  • Towards Versal-based Healthcare Federated Learning for Image Registration, Giuseppe Sorrentino, Marco Domenico Santambrogio and Davide Conficconi, Politecnico di Milano

Presentation and Poster Logistics

Please check the program to align your travel plans. If there is any risk that you might have travel complications, please let the Program Chair/Workshop Chair know ASAP!
Regular paper sessions:
  • Each full paper has a 25mins slot: 1.5min transition and intro + 20min talk + 3.5min Q/A.
  • Each short paper has a 10mins slot: 1.5min transition and intro + 8.5min talk, no Q/A. Each short paper will have to present a poster as well.
  • Watch for an email from your session chair and send them a short bio for introduction.
  • There will be a conference laptop for presentations. Please work with your session chair to upload and test your slides before your session starts. If you prefer to using your own laptop, please inform your session chair beforehand.
  • Best paper award: A selection committee will attend the presentation of all three best paper candidates, and announce the decision during the workshop closing and award ceremony. There will be a $500 cash award for the final best paper.
Panel-like special sessions:
  • 5min transition and intro
  • 1 hour pitch presentation: each speaker has about 15min, with 4 speakers in a session
  • 45min panel discussion, Q/A from audience
Posters:
  • RAW will provide easels with double-sided 4x8 feet cork boards, and push pins/clips for the posters. It’s recommended to print your poster no larger than an A0 paper size (841 x 1189 mm or 33.1 x 46.8 in).
  • It’s also recommended to print your poster beforehand and bring it to the workshop.
  • Here are some best practices on how to prepare a poster.
  • Best poster award: Each attendee will be given a ballot and vote for the best poster after they visit all the posters. The final best poster will be announced during the workshop closing and award ceremony. There will be a $500 cash award for the final best poster.

Topics of interest

Applications of Reconfigurable Architectures

  • ML/AI Acceleration
  • Big Data Analytics Acceleration
  • Applications in FinTech
  • Applications in Organic Computing, Biologically-Inspired Solutions
  • Applications in Computational Genomics and Healthcare
  • Applications in Autonomous Driving
  • Applications in Digital Media and Entertainment
  • Applications in HPC and Datacenters
  • Applications in Edge Devices and IoT Devices
  • Other Novel Use of Commercial FPGAs

Reconfigurable System Architectures & CAD Support

  • Domain-Specific Architectures and Overlay
  • Coarse-Grained Reconfigurable Architectures
  • Specialized Memory Systems including Volatile, Non-Volatile, and Hybrid Memory Subsystems
  • Near Data Reconfigurable Architectures and Systems (e.g., SmartNIC, SmartSSD)
  • Reconfigurable Datacenters and Cloud
  • FPGA-based MPSoC Architectures and Systems
  • Emerging Technologies (e.g., Optical Models, 3D Interconnects, Devices)
  • Other Evolvable, Adaptable, or Autonomous Reconfigurable Computing Systems
  • Low-Level CAD Support for the above Architectures and Systems
  • Critical Issues (Security, Reliability, Fault-Tolerance)

Software Programmability and Tool Support

  • Domain-Specific Languages and Compilers
  • High-Level Synthesis
  • System-Level Synthesis
  • Runtime Systems
  • Operating Systems and Virtualization
  • Debugging and Verification Tools
  • Runtime Reconfiguration Models
  • Partial Reconfiguration Techniques
  • Fast Simulation, Prototyping, and Profiling Tools
  • Other Tool Support to Facilitate Software-Defined Reconfigurable Computing

Call for Ph.D. Forum New!

RAW now accepts Ph.D. Forum Submissions! Accepted submissions will have a chance to present a poster in RAW 2024.

Ph.D. Forum Submission Guidelines

Submissions should be made online at this link. Please upload a single PDF file that has the following:
  • Title of your Ph.D. Forum submission
  • Name list of Ph.D. student and their advisor(s) with their affiliations
  • An extended abstract of up to 2 pages excluding figures and references

  • RAW 2024 Ph.D. Forum contact: Peipei Zhou, University of Pittsburgh, peipei.zhou@pitt.edu

    Submission deadline: May 7, 2024, 11.59 PM AOE

    Paper Submission

    Submission Rounds

    This year, for the first time, RAW will have two submission rounds. An early submission deadline on November 3rd will be followed by a second submission at the end of January. IMPORTANT NOTE: the two submission rounds are strictly independent chances for submission. Not having submitted for the first round does not prevent a second round submission.

    Publication and ACM TRETS Special Issue

    IEEE CS Press will publish the IPDPS symposium and workshop abstracts as a printed volume. Proceedings of the workshops are distributed at the conference and are submitted for inclusion in the IEEE Xplore Digital Library after the conference. We will also invite top papers from the workshop to extend their work and submit to the ACM TRETS special issue on RAW 2024.

    Submission Rules

    All manuscripts will be reviewed by at least three members of the program committee, with a single-blind review process. Submissions should be a complete manuscript or, in special cases, may be a summary of relevant work. There are two types of manuscripts: 1) full papers (up to 6 pages) and 2) short papers (up to 4 pages). Both manuscripts should follow the IEEE conference style: single-spaced, double-column pages using 10-point size font on 8.5X11 inch pages. The page limits exclude references and both manuscripts can include up to 2 pages of references. A conformant LaTeX template is available here. Overleaf users can find the LaTeX template here. A Microsoft Word template is available here.

    Submission Link

    Papers are to be submitted through Linklings. Please choose “Workshop: RAW 2024 Round 2". All papers must be submitted electronically in PDF format. Submitted papers should not have appeared in or be under submission for a different workshop, conference or journal. It is also expected that all accepted papers (full or short) will be presented at the workshop by one of the authors.

    Reviewer Conflict Policy

    During paper submission (in “Conflicts > My Conflicts”), all author(s) conflicts must be registered with all possible program committee members. Conflicts are defined as all relationships that would prevent a reviewer from objectively evaluating the submitted work. This includes, but is not limited to, having within the past 5 years, 1) co-authored a publication, or 2) shared a funding award, and 3) shared at least one institutional affiliation. Note: if a conflict is declared (or left undeclared) in an attempt to manipulate the review process, the submission may be rejected.

    Artifact Evaluation


    RAW 2024 will continue the experimental Artifact Evaluation (AE) initiated in RAW 2023. Authors of accepted papers at RAW 2024 can optionally participate in the AE process to formally describe supporting materials(code, data, models, workflows, results).
    Artifacts are digital objects that were created by the authors as part of the research or experiments performed with the submitted work. Examples of artifacts are:
  • Software: models, source code, scripts, Makefiles, container images (like Docker files), etc.
  • Hardware: Verilog, VHDL, schematics, CAD tools, flows, etc.
  • Data: spreadsheets, databases, binary files, design sets, etc.
  • High-quality artifacts are as important as the manuscript itself. The goal of submitting artifacts promotes the availability and reproducibility of the experimental results and data such that other researchers can repeat experiments and replicate results with less effort.
    Note that this submission is voluntary and will not influence the final decision regarding the papers. The goal is to help the authors validate experimental results from their accepted papers by an independent AE Committee (AEC) in a collaborative way while helping readers find articles with available (i.e., publicly accessible in an archival repository), functional (i.e., consistent, documented, and reusable), and validated (i.e., main results from the paper) artifacts. Each submitted artifact is evaluated by at least two members of the AEC. During the process, authors and evaluators are allowed to communicate anonymously with each other to overcome technical difficulties. Ideally, we hope to see all submitted artifacts successfully pass the artifact evaluation. More details on the AE process will follow. Finally, we are seeking volunteers to take part of the AE Committee. If you are interested in taking part of this initiative please fill out this form .

    To submit your artifacts please use this linklings site

    Publication

    IEEE CS Press will publish the IPDPS symposium and workshop abstracts as a printed volume. Proceedings of the workshops are distributed at the conference and are submitted for inclusion in the IEEE Xplore Digital Library after the conference.

    Important Dates

    First submission deadline: November 3, 2023
    Decision notification: December 18, 2023
    Second submission deadline: February 5, 2024 February 9, 2024

    Decision notification: March 9, 2024
    Camera-Ready papers due: March 20, 2024

    Camera-ready Instructions

    Detailed instructions are available in the IPDPS 2024 Author Resources webpage. The paper ID is the same as your paper submission ID (see email).
    The submission deadline for RAW workshop papers is Mar 20; IPDPS extended five more days for RAW. Full papers can include up to 8 pages (including references) by default, and purchase up to 2 additional pages (i.e., up to 10 pages in total) in the proceedings at USD$200 per page at the time you register.
    Short papers can include up to 6 pages (including references) and are not eligible to purchase additional pages. Posters can include up to 1 page (including references) and are not eligible to purchase additional pages.

    Registration Information

    Registration link is here. The advance registration deadline is Mar 31. Authors and attendees are encouraged to register and participate in the entire IPDPS conference. However, if you plan to attend the RAW workshop only, you can register for the “One Day Workshop” option, which will cover our two-day RAW workshop.
    For RAW paper authors: at least one author must be registered for the workshop by Mar 31 in order for the paper to be published in the proceedings. It must be a full registration (i.e., non-student registration), unless the sole author of the paper is a student.

    Visa

    If you need visa to travel to USA, detailed instructions to request a visa letter is available in the VISA LETTERS section here.

    Hotel Information

    The conference hotel is Hyatt Regency with an IPDPS 2024 group rate of $229 per night (Single/Double) (+ tax & fee @ ~17%). The booking link is here and the cut-off time is May 3, 5pm PT.

    Organization

    Workshop Chair

    • Marco Domenico Santambrogio, Politecnico di MIlano, Italy

    Program Chair

    • Zhenman Fang, Simon Fraser University, Canada

    Steering Committee

    • Juergen Becker, Karlsruhe Institute of Technology, Germany
    • Viktor K. Prasanna, University of Southern California, USA
    • Ramachandran Vaidyanathan, Louisiana State University, USA
    • Marco Domenico Santambrogio, Politecnico di MIlano, Italy

    Steering Chair

    • Viktor K. Prasanna, University of Southern California, USA

    Artifacts Chair

    • Davide Conficconi, Politecnico di Milano, Italy

    Finance Chair

    • Andrew Schmidt, AMD, USA

    PhD Forum Chair

    • Peipei Zhou, University of Pittsburgh, USA

    Publicity Co-Chairs

    • Brian Veale, IBM, USA
    • Christian Pilato, Politecnico di Milano, Italy

    Webmaster

    • Francesco Peverelli, Politecnico di Milano, Italy

    Program Committee

    • Aman Arora, Arizona State University
    • Bruce Cockburn, University of Alberta
    • Chen Zhang, Shanghai Jiao Tong University
    • Cheng Tan, Google
    • Christian Hochberger, TU Darmstadt
    • Christian Pilato, Politecnico di Milano
    • Davide Conficconi, Politecnico di Milano
    • Diana Goehringer, TU Dresden
    • Dimitrios Soudris, National Technical University of Athens
    • Dionisios Pnevmatikatos, National Technical University of Athens
    • Francisco Fons Lluis, Huawei
    • Hayden Kwok-Hay So, University of Hong Kong
    • Jason Anderson, University of Toronto
    • Jianyi Cheng, University of Cambridge
    • Jim Hwang, AMD
    • Kang Zhao, Beijing University of Posts and Telecommunications
    • Kazushi Kawamura, Tokyo Institute of Technology
    • Lana Josipovic, ETH Zurich
    • Liqiang Lu, Zhejiang University
    • Marco Domenico Santambrogio, Politecnico di Milano
    • Mario Porrmann, Osnabrueck University
    • Martin Herbordt, Boston University
    • Martin Langhammer, Intel
    • Michael Huebner, Brandenburg University of Technology Cottbus
    • Muhammad Ali Siddiqi, Lahore University of Management Sciences
    • Nithin George, Intel
    • Oliver Sinnen, University of Auckland
    • Peipei Zhou, University of Pittsburgh
    • Qiang Liu, Tianjin University
    • Ray Cheung, City University of Hong Kong
    • Ramachandran Vaidyanathan, Louisiana State University
    • Sergiu Mosanu, Micron Technology
    • Shouyi Yin, Tsinghua University
    • Steve Wilton, University of British Columbia
    • Tomohiro Ueno, RIKEN Center for Computational Science
    • Viktor Prasanna, University of Southern California
    • Wei Zhang, Hong Kong University of Science and Technology
    • Wenyi Feng, Ouster
    • Young-kyu Choi, Inha University
    • Yuichiro Shibata, Nagasaki University
    • Yukinori Sato, Toyohashi University of Technology
    • Zeke Wang, Zhejiang University
    • Zhenman Fang, Simon Fraser University

    Artifacts Evaluation Committee

    • Alberto Zeni, Politecnico di Milano
    • Amit Samanta, University of Utah
    • Fangzhou (Alec) Lu, Simon Fraser University
    • Filippo Carloni, Politecnico di Milano
    • Francesco Ratto, Università degli Studi di Sassari
    • Giuseppe Sorrentino, Politecnico di Milano
    • Harisankar Sadasivan, AMD
    • Marco Venere, Politecnico di Milano

    Golden Sponsor



    Silver Sponsor