33rd Reconfigurable Architectures Workshop
Official website: raw.necst.it
May 25th-26th 2026. New Orleans, USA

The 33rd Reconfigurable Architectures Workshop (RAW 2026) will be held in New Orleans, USA in May 2026. RAW 2026 is associated with the 40th Annual IEEE International Parallel & Distributed Processing Symposium (IEEE IPDPS 2026) and is sponsored by the IEEE Computer Society and the Technical Committee on Parallel Processing. The workshop is one of the major meetings for researchers to present ideas, results, and on-going research on both theoretical and practical advances in Reconfigurable Computing.

A reconfigurable computing environment is characterized by the ability of underlying hardware architectures or devices to rapidly alter (often on the fly) the functionalities of their components and the interconnection between them to suit the problem at hand. The area has a rich theoretical tradition and wide practical applicability. There are several commercially available reconfigurable platforms (FPGAs and coarse-grained devices) and many modern applications (including embedded systems and HPC) use reconfigurable subsystems. An appropriate mix of theoretical foundations and practical considerations, including algorithms, applications, architectures, technologies, systems, programming models and tools, is essential to fully exploit the possibilities offered by reconfigurable computing. The Reconfigurable Architectures Workshop aims to provide a forum for creative and productive interaction for researchers and practitioners in the area.

Topics of interest

RAW 2026 Call for Papers

TRETS Special Issue on RAW 2026

After two successful years, we will continue to push for a journal special issue. For RAW 2026, we are collaborating with ACM TRETS to organize a journal special issue. We will invite top papers from the RAW 2026 program to extend their work and submit to the ACM TRETS special issue on RAW 2026.

Submission of Papers

All manuscripts will be reviewed by at least three members of the program committee, with a single-blind review process. Submissions may be full papers (up to 6 pages) or short papers (up to 4 pages), formatted using the IEEE conference template. : single-spaced, double-column pages using 10-point size font on 8.5X11 inch pages. The page limits exclude references and both manuscripts can include up to 2 pages of references. Templates are available:
LaTeX: here
Overleaf: here
Word: here

Papers are to be submitted through Linkings. All papers must be submitted electronically in PDF format. Submitted papers should not have appeared in or be under submission for a different workshop, conference or journal. It is also expected that all accepted papers (full or short) will be presented at the workshop by one of the authors.

Publication and Journal Special Issue

IEEE CS Press will publish the IPDPS symposium and workshop abstracts as a printed volume. Proceedings of the workshops are distributed at the conference and submitted to IEEE Xplore. Top papers will be invited to submit extended versions to the ACM TRETS special issue on RAW 2026.

Awards

RAW 2026 will have 3 different awards:

• Best paper (selected after the presentation of the 3 best paper candidates)
• Best poster (selected among all the poster presentations at RAW 2026)

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Call for Ph.D. Forum

The Reconfigurable Architectures Workshop (RAW) will continue with its third edition of the Ph.D Forum. The forum is an excellent opportunity for PhD students to present their research and engage with the broader reconfigurable computing community. PhD students conducting research in reconfigurable computing and related fields are invited to participate in the poster session, where they can share their work, exchange ideas, and receive feedback from experienced researchers and peers.

To apply for the forum, prospective participants will be required to submit a two-page extended abstract using IEEE conference standard template. Please highlight the student and the advisor(s) in the submission.
Deadline: Apr 20, 2026 May 4, 2026

How: send an email with subject: "[RAW 2026 - PhD Forum]" to neha.prakriya@amd.com

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Artifact Evaluation

RAW 2026 will continue the experimental Artifact Evaluation (AE) initiated in RAW 2023. Authors of accepted papers at RAW 2026 can optionally participate in the AE process to formally describe supporting materials (code, data, models, workflows, results).

Artifacts are digital objects that were created by the authors as part of the research or experiments performed with the submitted work. Examples of artifacts are:

• Software: models, source code, scripts, Makefiles, container images (like Docker files), etc.
• Hardware: Verilog, VHDL, schematics, CAD tools, flows, etc.
• Data: spreadsheets, databases, binary files, design sets, etc.

High-quality artifacts are as important as the manuscript itself. The goal of submitting artifacts promotes the availability and reproducibility of the experimental results and data such that other researchers can repeat experiments and replicate results with less effort.

Note that this submission is voluntary and will not influence the final decision regarding the papers. The goal is to help the authors validate experimental results from their accepted papers by an independent AE Committee (AEC) in a collaborative way while helping readers find articles with available (i.e., publicly accessible in an archival repository), functional (i.e., consistent, documented, and reusable), and validated (i.e., main results from the paper) artifacts.

Each submitted artifact is evaluated by at least two members of the AEC. During the process, authors and evaluators are allowed to communicate anonymously with each other to overcome technical difficulties. Ideally, we hope to see all submitted artifacts successfully pass the artifact evaluation. More details on the AE process will follow, and in the meantime check the FAQ.

Finally, we are seeking volunteers to take part in the AE Committee. If you are interested in taking part in this initiative please consider submitting your candidacy or those of your students. Please contact the Program Chairs. A form will be shared ahead of time.

Program

Monday, May 25th

8:30 – 8:45	Registration
8:45 – 9:00	Opening Session
9:00 – 10:00	Keynote — TBA
10:00 – 10:30	Coffee Break
Datacenters and High Performance Reconfigurable Architectures — Session Chair: TBA
10:30 – 11:00	RAW-09	100 Gbps Hash-Based Reconfigurable Pattern Matching Best Paper Candidate	Magnus Östgren, Anna-Maria Unterberger, Ioannis Sourdis	Regular
11:00 – 11:30	RAW-08	Using FPGA-based Network-Attached Accelerators for Energy-Efficient AI Training in HPC Datacenters	Niklas Schelten, Steffen Christgau, Merit Hutzler, Philipp Kreowsky, Marco de Lucia, Bettina Schnor, Hannes Signer, Johannes Spazier, Benno Stabernack, Serhii Yahdzhyiev	Regular
11:30 – 11:45	RAW-17	From Algorithm to RTL: A Comparative Study of Compiler-Driven and LLM-Driven FPGA Design Flows	Md Mahfuzul Haque Gazi, Rickard Ewetz, Hao Zheng, Md Rubel Ahmed	Short
12:00 – 13:30	Lunch Break (not included)
Exploring AI Accelerators in the Wild Reconfigurable World — Session Chair: TBA
13:30 – 14:00	RAW-18	Configurable Architecture Design Automation (CADA) – Enabling Efficient, Dynamically Reconfigurable Systems Best Paper Candidate	Tim Ling, Jack Burd, Dejan Markovic	Regular
14:00 – 14:30	RAW-10	A Power-Centric Methodology to Characterize Edge AI SoC with Limited Telemetry Capabilities Best Paper Candidate	Giulio Mantovi, Davide Paltrinieri, Giuseppe Sorrentino, Christian Pilato, Davide Conficconi	Regular
14:30 – 15:00	RAW-15	Design Space Exploration of Convolutional Neural Network Accelerators for Predictive Maintenance	Florian Rokohl, Sudatta Mondal, Edris Zaman Farsa, Marc Reichenbach	Short
15:00 – 15:30	Coffee Break
Posters and PhD Forum — Session Chair: Neha Prakriya
15:30 – 17:00	Introduction for Poster Session
15:30 – 17:00	RAW-03	Comparing High-Level Synthesis and RTL for Simple FPGA Kernels – Revisited	Vinicius R. Fertrin, Christopher D. Gill, Roger D. Chamberlain	Poster
	RAW-04	Hokidachi: Low-Latency Random Forest Inference on FPGAs through Full Horizontal Parallelism	Andrea Bellocci, Alessandro Verosimile, Marco Domenico Santambrogio	Poster
	RAW-06	A Minimal and Jitter-Free FPGA Telemetry Core for Cycle-Accurate Determinism in Real-Time Systems	Ceren Korkmaz, Busra Bulut, Ayse Yayla	Poster
	RAW-07	A Lightweight Slow Control Interlock System targeting the European GateMate FPGA	Daniel Anders, Vitalii Burtsev, Daniele Passaretti, Christof Pfannenmueller, Fabian Lurz, Thilo Pionteck	Poster
	RAW-11	End-to-end Reconfigurable Rack-Scale Systems	Cullen Bash, Ray Beausoleil, Pedro Bruel, Chris Davidson, Aditya Dhakal, Rolando Pablo Hong Enriquez, Marco Fiorentino, Jim Ignowski, Keith McAuliffe, Dejan Milojicic, Alok Mishra, Viyom Mittal, Chandrakant Patel, Sudeep Pasricha, Pavana Prakash, Gourav Rattihalli, Duncan Roweth, Samantika Sury, Bassem Tossoun, Alex Veprinsky, Jason Zeiler	Poster
	RAW-12	High-Performance Hyperspectral Brain Tumor Analysis on Versal ACAP	Dismas Ezechukwu, Mark Sears, Chenfeng Zhao, Dinesh Bhatia	Poster
	RAW-13	A Hierarchical Methodology for Hardware Design Exploration of Mathematical Kernels	Angelos Ioannou, Mario Vega, Fabien Chaix, Dania Mosuli, Blair Reasoner, Tan Nguyen, Xiaokun Yang, John Shalf, Doru Thom Popovici	Poster
	RAW-19	A Persistent-State Dataflow Accelerator for Memory-Bound Linear Attention Decode on FPGA	Neelesh Gupta, Peter Wang, Rajgopal Kannan, Viktor Prasanna	Poster
	—	PhD Forum 1		PhD Forum
	—	PhD Forum 2		PhD Forum
End of Day 1

Tuesday, May 26th

8:30 – 9:00	Registration
10:00 – 10:30	Coffee Break
10:30 – 12:00	Keynote — TBA
12:00 – 13:30	Lunch Break (not included)
From Methodology to Implementations: A Journey to the Center of the FPGA World — Session Chair: TBA
13:30 – 14:00	RAW-14	Programming Domain-Specific FPGA Hardblocks from HLS: An RTL Blackbox Approach	Ruthwik Reddy Sunketa, Jeevesh Choudhury, Aman Arora	Regular
14:00 – 14:30	RAW-02	Pipelined FPGA Implementation of the QP-DYN Cipher with Scalable Dynamical System Parallelism	Paolo Palazzari, Luigi Accardi, Pasquale Tommasino, Alessandro Trifiletti	Regular
14:30 – 15:00	Awards and Closing Ceremony
15:00 – 15:30	Coffee Break
17:00 – 18:10	Panel: "Extending the lifespan of supercomputers: Experience, Challenges and Opportunities" — by IPDPS
18:10 – 18:30	TCPP Announcement and Awards

Regular  Short  Poster  PhD Forum  Best Paper Candidate

Organization

Workshop Chair

• Marco Domenico Santambrogio, Politecnico di Milano, Italy

Program Co-Chairs

• Atefeh Sohrabizadeh, NVIDIA, California
• Davide Conficconi, Politecnico di Milano, Italy

Steering Committee

• Juergen Becker, Karlsruhe Institute of Technology, Germany
• Viktor K. Prasanna, University of Southern California, USA
• Ramachandran Vaidyanathan, Louisiana State University, USA
• Marco D. Santambrogio, Politecnico di Milano, Italy

Steering Chair

• Viktor K. Prasanna, University of Southern California, USA

Artifact Evaluation Chair

• Francesco Peverelli, Huawei Research, Switzerland

PhD Forum Chair

• Neha Prakriya, AMD

Publicity Co-Chairs

• Brian Veale, IBM, USA
• Christian Pilato, Politecnico di Milano, Italy

Webmaster

• Laura Ginestretti, Politecnico di Milano, Italy