32nd Reconfigurable Architectures Workshop
Official website:
June 3rd-4th 2025. Milano, Italy

The 32nd Reconfigurable Architectures Workshop (RAW 2025) will be held in Milano, Italy on june 3rd and 4th 2025. RAW 2025 is associated with the 39th Annual IEEE International Parallel & Distributed Processing Symposium (IEEE IPDPS 2025) and is sponsored by the IEEE Computer Society and the Technical Committee on Parallel Processing. The workshop is one of the major meetings for researchers to present ideas, results, and on-going research on both theoretical and practical advances in Reconfigurable Computing.

A reconfigurable computing environment is characterized by the ability of underlying hardware architectures or devices to rapidly alter (often on the fly) the functionalities of their components and the interconnection between them to suit the problem at hand. The area has a rich theoretical tradition and wide practical applicability. There are several commercially available reconfigurable platforms (FPGAs and coarse-grained devices) and many modern applications (including embedded systems and HPC) use reconfigurable subsystems. An appropriate mix of theoretical foundations and practical considerations, including algorithms architectures, applications, technologies and tools, is essential to fully exploit the possibilities offered by reconfigurable computing. The Reconfigurable Architectures Workshop aims to provide a forum for creative and productive interaction for researchers and practitioners in the area.

Topics of interest

Applications of Reconfigurable Architectures

  • ML/AI Acceleration
  • Big Data Analytics Acceleration
  • Applications in FinTech
  • Applications in Organic Computing, Biologically-Inspired Solutions
  • Applications in Computational Genomics and Healthcare
  • Applications in Autonomous Driving
  • Applications in Digital Media and Entertainment
  • Applications in HPC and Datacenters
  • Applications in Edge Devices and IoT Devices
  • Other Novel Use of Commercial FPGAs

Reconfigurable System Architectures & CAD Support

  • Domain-Specific Architectures and Overlay
  • Coarse-Grained Reconfigurable Architectures
  • Specialized Memory Systems including Volatile, Non-Volatile, and Hybrid Memory Subsystems
  • Near Data Reconfigurable Architectures and Systems (e.g., SmartNIC, SmartSSD)
  • Reconfigurable Datacenters and Cloud
  • FPGA-based MPSoC Architectures and Systems
  • Emerging Technologies (e.g., Optical Models, 3D Interconnects, Devices)
  • Other Evolvable, Adaptable, or Autonomous Reconfigurable Computing Systems
  • Low-Level CAD Support for the above Architectures and Systems
  • Critical Issues (Security, Reliability, Fault-Tolerance)

Software Programmability and Tool Support

  • Domain-Specific Languages and Compilers
  • High-Level Synthesis
  • System-Level Synthesis
  • Runtime Systems
  • Operating Systems and Virtualization
  • Debugging and Verification Tools
  • Runtime Reconfiguration Models
  • Partial Reconfiguration Techniques
  • Fast Simulation, Prototyping, and Profiling Tools
  • Other Tool Support to Facilitate Software-Defined Reconfigurable Computing

Paper Submission

Submission Rounds

This year RAW will have a single submission round at the end of January.

Submission Rules

All manuscripts will be reviewed by at least three members of the program committee, with a single-blind review process. Submissions should be a complete manuscript or, in special cases, may be a summary of relevant work. There are two types of manuscripts: 1) full papers (up to 6 pages) and 2) short papers (up to 4 pages). Both manuscripts should follow the IEEE conference style: single-spaced, double-column pages using 10-point size font on 8.5X11 inch pages. The page limits exclude references and both manuscripts can include up to 2 pages of references. A conformant LaTeX template is available here. Overleaf users can find the LaTeX template here. A Microsoft Word template is available here.

Submission LinkComing Soon

Reviewer Conflict Policy

During paper submission (in “Conflicts > My Conflicts”), all author(s) conflicts must be registered with all possible program committee members. Conflicts are defined as all relationships that would prevent a reviewer from objectively evaluating the submitted work. This includes, but is not limited to, having within the past 5 years, 1) co-authored a publication, or 2) shared a funding award, and 3) shared at least one institutional affiliation. Note: if a conflict is declared (or left undeclared) in an attempt to manipulate the review process, the submission may be rejected.


IEEE CS Press will publish the IPDPS symposium and workshop abstracts as a printed volume. Proceedings of the workshops are distributed at the conference and are submitted for inclusion in the IEEE Xplore Digital Library after the conference.

Important DatesComing Soon


Workshop Chair

  • Marco Domenico Santambrogio, Politecnico di MIlano, Italy

Program Co-Chairs

  • Zhenman Fang, Simon Fraser University, Canada
  • Davide Conficconi, Politecnico di MIlano, Italy

Steering Committee

  • Juergen Becker, Karlsruhe Institute of Technology, Germany
  • Viktor K. Prasanna, University of Southern California, USA
  • Ramachandran Vaidyanathan, Louisiana State University, USA
  • Marco Domenico Santambrogio, Politecnico di MIlano, Italy

Steering Chair

  • Viktor K. Prasanna, University of Southern California, USA


  • Francesco Peverelli, Politecnico di Milano, Italy

Program CommitteeComing Soon