31st Reconfigurable Architectures Workshop
Official website:
May 27th-28th 2024. San Francisco, California, USA

The 31st Reconfigurable Architectures Workshop (RAW 2024) will be held in San Francisco, California USA on May 27th and 28th 2024. RAW 2024 is associated with the 38th Annual IEEE International Parallel & Distributed Processing Symposium (IEEE IPDPS 2024) and is sponsored by the IEEE Computer Society and the Technical Committee on Parallel Processing. The workshop is one of the major meetings for researchers to present ideas, results, and on-going research on both theoretical and practical advances in Reconfigurable Computing.

A reconfigurable computing environment is characterized by the ability of underlying hardware architectures or devices to rapidly alter (often on the fly) the functionalities of their components and the interconnection between them to suit the problem at hand. The area has a rich theoretical tradition and wide practical applicability. There are several commercially available reconfigurable platforms (FPGAs and coarse-grained devices) and many modern applications (including embedded systems and HPC) use reconfigurable subsystems. An appropriate mix of theoretical foundations and practical considerations, including algorithms architectures, applications, technologies and tools, is essential to fully exploit the possibilities offered by reconfigurable computing. The Reconfigurable Architectures Workshop aims to provide a forum for creative and productive interaction for researchers and practitioners in the area.

Topics of interest

Applications of Reconfigurable Architectures

  • ML/AI Acceleration
  • Big Data Analytics Acceleration
  • Applications in FinTech
  • Applications in Organic Computing, Biologically-Inspired Solutions
  • Applications in Computational Genomics and Healthcare
  • Applications in Autonomous Driving
  • Applications in Digital Media and Entertainment
  • Applications in HPC and Datacenters
  • Applications in Edge Devices and IoT Devices
  • Other Novel Use of Commercial FPGAs

Reconfigurable System Architectures & CAD Support

  • Domain-Specific Architectures and Overlay
  • Coarse-Grained Reconfigurable Architectures
  • Specialized Memory Systems including Volatile, Non-Volatile, and Hybrid Memory Subsystems
  • Near Data Reconfigurable Architectures and Systems (e.g., SmartNIC, SmartSSD)
  • Reconfigurable Datacenters and Cloud
  • FPGA-based MPSoC Architectures and Systems
  • Emerging Technologies (e.g., Optical Models, 3D Interconnects, Devices)
  • Other Evolvable, Adaptable, or Autonomous Reconfigurable Computing Systems
  • Low-Level CAD Support for the above Architectures and Systems
  • Critical Issues (Security, Reliability, Fault-Tolerance)

Software Programmability and Tool Support

  • Domain-Specific Languages and Compilers
  • High-Level Synthesis
  • System-Level Synthesis
  • Runtime Systems
  • Operating Systems and Virtualization
  • Debugging and Verification Tools
  • Runtime Reconfiguration Models
  • Partial Reconfiguration Techniques
  • Fast Simulation, Prototyping, and Profiling Tools
  • Other Tool Support to Facilitate Software-Defined Reconfigurable Computing

Paper Submission

Submission Rounds

This year, for the first time, RAW will have two submission rounds. An early submission deadline on November 3rd will be followed by a second submission at the end of January. IMPORTANT NOTE: the two submission rounds are strictly independent chances for submission. Not having submitted for the first round does not prevent a second round submission.

Publication and ACM TRETS Special Issue

IEEE CS Press will publish the IPDPS symposium and workshop abstracts as a printed volume. Proceedings of the workshops are distributed at the conference and are submitted for inclusion in the IEEE Xplore Digital Library after the conference. We will also invite top papers from the workshop to extend their work and submit to the ACM TRETS special issue on RAW 2024.

Submission Rules

All manuscripts will be reviewed by at least three members of the program committee, with a single-blind review process. Submissions should be a complete manuscript or, in special cases, may be a summary of relevant work. There are two types of manuscripts: 1) full papers (up to 6 pages) and 2) short papers (up to 4 pages). Both manuscripts should follow the IEEE conference style: single-spaced, double-column pages using 10-point size font on 8.5X11 inch pages. The page limits exclude references and both manuscripts can include up to 2 pages of references. A conformant LaTeX template is available here. Overleaf users can find the LaTeX template here. A Microsoft Word template is available here.

Submission Link

Papers are to be submitted through Linklings. Please choose “Workshop: RAW 2024 Round 2". All papers must be submitted electronically in PDF format. Submitted papers should not have appeared in or be under submission for a different workshop, conference or journal. It is also expected that all accepted papers (full or short) will be presented at the workshop by one of the authors.

Reviewer Conflict Policy

During paper submission (in “Conflicts > My Conflicts”), all author(s) conflicts must be registered with all possible program committee members. Conflicts are defined as all relationships that would prevent a reviewer from objectively evaluating the submitted work. This includes, but is not limited to, having within the past 5 years, 1) co-authored a publication, or 2) shared a funding award, and 3) shared at least one institutional affiliation. Note: if a conflict is declared (or left undeclared) in an attempt to manipulate the review process, the submission may be rejected.

Artifact Evaluation

RAW 2024 will continue the experimental Artifact Evaluation (AE) initiated in RAW 2023. Authors of accepted papers at RAW 2024 can optionally participate in the AE process to formally describe supporting materials(code, data, models, workflows, results).
Artifacts are digital objects that were created by the authors as part of the research or experiments performed with the submitted work. Examples of artifacts are:
  • Software: models, source code, scripts, Makefiles, container images (like Docker files), etc.
  • Hardware: Verilog, VHDL, schematics, CAD tools, flows, etc.
  • Data: spreadsheets, databases, binary files, design sets, etc.
  • High-quality artifacts are as important as the manuscript itself. The goal of submitting artifacts promotes the availability and reproducibility of the experimental results and data such that other researchers can repeat experiments and replicate results with less effort.
    Note that this submission is voluntary and will not influence the final decision regarding the papers. The goal is to help the authors validate experimental results from their accepted papers by an independent AE Committee (AEC) in a collaborative way while helping readers find articles with available (i.e., publicly accessible in an archival repository), functional (i.e., consistent, documented, and reusable), and validated (i.e., main results from the paper) artifacts. Each submitted artifact is evaluated by at least two members of the AEC. During the process, authors and evaluators are allowed to communicate anonymously with each other to overcome technical difficulties. Ideally, we hope to see all submitted artifacts successfully pass the artifact evaluation. More details on the AE process will follow.
    Finally, we are seeking volunteers to take part of the AE Committee. If you are interested in taking part of this initiative please fill out this form .


    IEEE CS Press will publish the IPDPS symposium and workshop abstracts as a printed volume. Proceedings of the workshops are distributed at the conference and are submitted for inclusion in the IEEE Xplore Digital Library after the conference.

    Important Dates

    First submission deadline: November 3, 2023
    Decision notification: December 18, 2023
    Second submission deadline: February 5, 2024 February 9, 2024

    Decision notification: March 15, 2024
    Camera-Ready papers due: March 29, 2024


    Workshop Chair

    • Marco Domenico Santambrogio, Politecnico di MIlano, Italy

    Program Chair

    • Zhenman Fang, Simon Fraser University, Canada

    Steering Committee

    • Juergen Becker, Karlsruhe Institute of Technology, Germany
    • Viktor K. Prasanna, University of Southern California, USA
    • Ramachandran Vaidyanathan, Louisiana State University, USA
    • Marco Domenico Santambrogio, Politecnico di MIlano, Italy

    Steering Chair

    • Viktor K. Prasanna, University of Southern California, USA

    Artifacts Chair

    • Davide Conficconi, Politecnico di Milano, Italy

    Finance Chair

    • Andrew Schmidt, AMD, USA

    PhD Forum Chair

    • Peipei Zhou, University of Pittsburgh, USA

    Publicity Co-Chairs

    • Brian Veale, IBM, USA
    • Christian Pilato, Politecnico di Milano, Italy


    • Francesco Peverelli, Politecnico di Milano, Italy

    Program Committee

    • Aman Arora, Arizona State University
    • Bruce Cockburn, University of Alberta
    • Chen Zhang, Shanghai Jiao Tong University
    • Cheng Tan, Google
    • Christian Hochberger, TU Darmstadt
    • Christian Pilato, Politecnico di Milano
    • Davide Conficconi, Politecnico di Milano
    • Diana Goehringer, TU Dresden
    • Dimitrios Soudris, National Technical University of Athens
    • Dionisios Pnevmatikatos, National Technical University of Athens
    • Francisco Fons Lluis, Huawei
    • Hayden Kwok-Hay So, University of Hong Kong
    • Jason Anderson, University of Toronto
    • Jianyi Cheng, University of Cambridge
    • Jim Hwang, AMD
    • Kang Zhao, Beijing University of Posts and Telecommunications
    • Kazushi Kawamura, Tokyo Institute of Technology
    • Lana Josipovic, ETH Zurich
    • Liqiang Lu, Zhejiang University
    • Marco Domenico Santambrogio, Politecnico di Milano
    • Mario Porrmann, Osnabrueck University
    • Martin Herbordt, Boston University
    • Martin Langhammer, Intel
    • Michael Huebner, Brandenburg University of Technology Cottbus
    • Muhammad Ali Siddiqi, Lahore University of Management Sciences
    • Nithin George, Intel
    • Oliver Sinnen, University of Auckland
    • Peipei Zhou, University of Pittsburgh
    • Qiang Liu, Tianjin University
    • Ray Cheung, City University of Hong Kong
    • Ramachandran Vaidyanathan, Louisiana State University
    • Sergiu Mosanu, Micron Technology
    • Shouyi Yin, Tsinghua University
    • Steve Wilton, University of British Columbia
    • Tomohiro Ueno, RIKEN Center for Computational Science
    • Viktor Prasanna, University of Southern California
    • Wei Zhang, Hong Kong University of Science and Technology
    • Wenyi Feng, Ouster
    • Young-kyu Choi, Inha University
    • Yuichiro Shibata, Nagasaki University
    • Yukinori Sato, Toyohashi University of Technology
    • Zeke Wang, Zhejiang University
    • Zhenman Fang, Simon Fraser University

    Artifacts Evaluation CommitteeComing Soon